( ESNUG 317 Item 9 ) --------------------------------------------- [5/13/99]
From: "Sean Atsatt" <seana@sierraimaging.com>
Subject: Watch Out! Dangerous ModelTech SDF Back-annotation Sim X Hole !!
Hi, John
What a life! Getting this when I'm trying to tape out a @#!&* ASIC!
We just ran across a serious hole in back annotated timing simulations
causing incorrect functional simulation. The problem occurs when your SDF
back annotation for a gate uses conditional iopath assignments and not all
conditions are covered. This happens quite naturally when you have an X
input.
Consider the case of a single gate implementing the function
Y <= (A1 and A2) or B
Suppose that at a specific point in time A1 = X, A2 = 0, B=0, and B
transitions from 0 to 1. In this event Y will transition from a 0 to a 1.
The question is what is the delay for this event given the following SDF
timing data for the B to Y path.
(COND A1==0 && A2==0 && B ==0 (IOPATH B Y(30:50:90)(20:30:50)))
(COND A1==0 && A2==0 && B ==1 (IOPATH B Y(31:51:91)(21:31:51)))
(COND A1==0 && A2==1 && B ==0 (IOPATH B Y(32:52:92)(22:32:52)))
(COND A1==0 && A2==1 && B ==1 (IOPATH B Y(33:53:93)(23:33:53)))
(COND A1==1 && A2==0 && B ==0 (IOPATH B Y(34:54:94)(24:34:54)))
(COND A1==1 && A2==0 && B ==1 (IOPATH B Y(35:55:95)(25:35:55)))
(COND A1==1 && A2==1 && B ==0 (IOPATH B Y(36:56:96)(26:36:56)))
(COND A1==1 && A2==1 && B ==1 (IOPATH B Y(37:57:97)(27:37:57)))
The answer is that the delay defaults to the built in delay of the gate.
But wait, what if all the built in delays are conditional as well and none
these conditions apply either because of the X input? The answer for MTI
(Model Technology Inc.) VHDL was 0 delay. A fully functional and correc
data path has the wrong delay and with no warning!. This issue was
particularly exacerbated by the fact that we have a large number of RAM's
generating X's on every clock cycle. How many paths in our design are being
simulated incorrectly?
The proposed IEEE 1497 spec for SDF supports a CONDELSE construct, but
neither my Library nor my Simulator support it yet. I talked with MTI
about this issue, and there response was that they were behaving according
to spec and that this was a library problem. This is true in the strictest
sense, however the few VITAL libraries that I have access to don't cover
all the 8 valued possibilities, (0,1,X,U,H.L,Z,-) used in std_logic. I
don't remember how the Verilog libraries I have used in the past handled
this. I think that the simulator has a responsibility to at least warn
the user when a back annotated net list has no applicable delay value for
a gate. Here are the suggestions I sent to MTI (no response yet from MTI).
1. Add a switch which enables a warning if there is no delay that can be
applied from the set of SDF conditionals for that path. (The default
model delay will never be correct in deep submicron.)
2. Add a switch which enables a warning if there is no conditional delay
in the SDF file and no conditional delay in the vital model that can be
applied. (This is what happened to us)
3. Add a switch which enables the selection of the most conservative delay
value out of the conditional set if none of the conditionals are met.
The most conservative solution would be to select the maximum of the
possible delays (assuming the X value was 1 or 0) if you were running
SDF Max and the Minimum of the possible delays if you were running SDF
min. This would be a reasonable solution that would overcome library
issues.
Since I have never run across this before I am wondering if it only shows up
in deep submicron (we're at 0.25) designs where second and third order
affects must be modeled in order to get accurate results.
Do any of your readers have experience with this? Do other simulators
generate warnings when they can find no valid conditional delay to apply?
Do other libraries specify the X conditions in the SDF? I'd be interested
to hear more on this in ESNUG.
- Sean Atsatt
Sierra Imaging
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