( ESNUG 317 Item 8 ) --------------------------------------------- [5/13/99]
From: Gzim Derti <gderti@intrinsix.com>
Subject: My DW/DC/Sim Nightmare Inferring Usable Pipelined Multipliers
John,
I've been trying to play with inferring pipelined multipliers using
DC but have run into a couple of road-blocks that I can't seem to
work around.
The code that I've generated is below.
library ieee, DW02;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use DW02.DW02_components.all;
--Include DesignWare library that contains piped mult components
entity pipemult is
port(
resetz : in std_logic;
clk : in std_logic;
ina_s : in signed(15 downto 0);
inb_s : in signed(15 downto 0);
pmult_s : out signed(31 downto 0)
);
end pipemult;
architecture rtl of pipemult is
signal tempmult_s : signed(31 downto 0);
begin
tempmult_s <= mult_4s(ina_s, inb_s, clk);
process(resetz, clk)
begin
if (resetz = '0') then
pmult_s <= (others => '0');
elsif (clk'event and clk = '1') then
pmult_s <= tempmult_s;
end if;
end process;
end rtl;
The trouble that I'm having is two-fold.
1) When I use the inferred version as above, the resultant gates
function as I assumed they would, but when I try and perform an
RTL simulation, the multiply function takes only 1 clock cycle
to complete, instead of the 4 that I requested. In checking the
DW02_components.vhd file supplied by Synopsys, I can see why this
is the case, there is no delay modeled in the mult_4s function.
So, I guess I need to ask if anyone else has tried to use the
INFERRED pipelined multiplier function mult_4s or other and
gotten RTL simulation to match gates???
2) When DC compiles the code above, it generates correct gates, but
there is no way to tell DC to create a RESETABLE pipeline. When
DC spins the gates, it uses whatever gates it deems necessary, and
since the call to the mult_4s only reference inputs, output, and
clock, there seems to be no way to tell DC that I want to be able
to RESET the pipeline. This would be of ENORMOUS benefit for
testability.
And yes, I know that I can do this all manually and then use
balance_registers to distribute the logic between the n-stages of
flops that I place in the RTL. I'm just trying to figure out why
Synopsys would let you do this if you can't match RTL and gate sims??
I don't know if anyone else my have run into this, but I had to ask.
As always, thanks much for ESNUG, John.
- Gzim Derti
Intrinsix Corp. Rochester, NY
|
|
