( ESNUG 317 Item 6 ) --------------------------------------------- [5/13/99]
From: gmann@ford.com (Greg Mann)
Subject: Five Lessons I Learned The Hard Way While Using DC 99.05
John,
I've been playing around with DC 99.05 quite a bit lately and thought I
should pass along what I've learned the hard way. Did you ever go into a
candy store as a child and see so many wonderful things and wanted to have
it all? But your Mom told you to pick just one thing. Well that might be
good advice when using new features in DC 99.05.
Synopsys version 99.05 has some nifty new features which are quite useful,
but also has some hidden "features" which can bite you -- especially if you
get too greedy and start using the nifty features all at the same time.
I'll mention some of the nifty features along with what's bitten me.
propagate_constraints:
The propagate_constraints command has already made my life much easier by
simplifying the application of constraints in a design hierarchy.
Constraints can be applied at a lower level of the hierarchy and then
propagated to the top level with the propagate_constraints command.
Propagate_constraints works as advertised and only as advertised. So be
sure to read the documentation. I had a case in which I segmented timing
paths using input and output delays on an internal pin. These constraints
are not propagated (yet--track STAR 69625). I was able to get around this
problem thanks to the the new "-through" option for timing exceptions.
Gated clock timing checks:
Design Compiler and PrimeTime now both provide for timing checks on gated
clocks. These timing checks can be controlled on a per-instance or
per-design basis. The catch is that Design Compiler and PrimeTime are
inconsistent in how they implement checks on gated clocks. So if you use
both tools, be sure to read the docs for each tool. My understanding is
that R&D is working to bring the tools more into line (read the release
notes for the latest PrimeTime release), but don't take anything for granted
yet at this point. Track ESTAR 69365 for this issue.
Design Budgeting:
Design Budgeting is a hot new feature which should be a vast improvement
over characterize when it comes to converging on a reasonable time budget.
It also budgets such things as fanout, etc. Apply top level constraints,
and the allocate_budgets command figures out a good set of constraints for
each sub-block which when met will guarantee that the top level constraints
are met. But be careful if your using other nifty features. If you have
gated clocks or exceptions with the "-through" option, the design budgeter
will completely ignore them. The result is that logic which gates clocks
may be under-constrained and logic along affected false paths will be over
constrained. Design budgeting is a great feature, but be careful if you're
getting fancy. Track STAR 69975 for the problem with ignoring
gated clocks.
Things that Got Broken in DC 99.05:
The syntax checker FATALs when you have exceptions in your script with the
"-through" option. It seems that the syntax checker guys kind of fell
asleep while the rest of Design Compiler moved forward. STAR 69179 has
been filed for this bug.
***This next one is BAD!!!***
The characterize command may convert an exception in the form
"set_false_path -from clk1 -to clk2 "
to
"set_false_path -to clk2"
in lower level blocks in your hierarchy. The result is that the lower level
block may now be completely unconstrained. This will happen in a case where
a design has multiple clocks (Test_clk & Sys_clk for example), but a lower
level module is only affected by the one clock. This problem is new with
99.05. The good news is that they already have a fix which will be
contained in an update which is due out at the end of May. I verified the
fix with a beta version of that patch.
Summary:
The 99.05 release of dc_shell is a big leap forward in a lot of ways, but
if you're feature greedy like I am, make sure you verify that the tool is
doing what it's supposed to. And listen to your Mom.
- Greg Mann
Ford Microelectronics Colorado Springs, CO
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