( ESNUG 316 Item 14 ) ---------------------------------------------- [4/8/99]
Subject: ( ESNUG 313 #1 ) Wall Street Curious About Altera/Synopsys Deal
> I am a securities analyst covering semiconductors at J.P. Morgan, and I
> spend a fair bit of my time on Altera, Xilinx, Lattice, and LSI Logic.
> Somebody recently suggested to me that I would probably learn a lot from
> ESNUG. Is it as simple as just asking to be added to the mailing list?
> If so, please do. ... I'd like to develop some contacts among designers
> so that I have some live people that I can ask about things like ...
> Do you have any suggestions about how I might find such people?
>
> - Terry Ragsdale
> J.P. Morgan
From: miller@symbol.com (Wayne Miller)
Hi John,
I think this is a novel idea, but it scares me a little to think how much
impact a few negative words might have on a company's market capitalization.
Since ESNUG represents user feedback, I think the information should help
balance the sales and marketing pitches...
But keep on the lookout. This past year at the Cadence User's Conference
in Texas, I was surprised to see three Wall Street types sitting in on a
Deep Sub-Micron session. With buy/sell recommendations up for grabs, I
started to wonder how accurate and "investor unbiased" the information we
received really was. I applaud Cadence for keeping the marketing in check,
but now that Wall Street sits in on these conferences, I'm not sure there
is no "spit and polish" on more and more of what is being offered to the
customers.
- Wayne Miller
Symbol Technologies
---- ---- ---- ---- ---- ---- ----
From: "Terry Ragsdale" <ragsdale_terry@jpmorgan.com>
John,
First, thanks for the posting in ESNUG 313. I hadn't really expected to
see my words appear there verbatim, but I certainly like the results! The
response has been tremendous. In fact, I've been so buried that I haven't
even gotten around to responding to all of the people who contacted me
after seeing the post in ESNUG. This is called a high-class problem.
Second, Synopsys and Altera made an announcement a week or so ago that I
don't understand, and I wonder if you or others have a view on it. My
understanding is that Synopsys has agreed to add the PLD-specific synthesis
stuff in FPGA Express to its Design Compiler tool so that ASIC designers
can easily target PLDs without changing their normal design flow. I assume
that means that Altera PLDs (Flex 10K, Flex 6000, and APEX) appear as
target silicon choices (this may not be the term of art, but hopefully you
get the idea) within Design Compiler. This seems sensible and consistent
with the way that PLDs and synthesis tools have been headed for some time.
The part I don't understand is why Synopsys is doing this _exclusively_ for
Altera? Wouldn't it be wiser to keep Synopsys a general tool? Or tuned
for each of the FPGA vendors? Why an _exclusive_ deal w/ Altera?
- Terry Ragsdale
J.P. Morgan
|
|
