( ESNUG 316 Item 10 ) ---------------------------------------------- [4/8/99]
Subject: ( ESNUG 313 #10 ) Analog Phase-Locked Loops In Verilog
> I am trying to build a Verilog model of an analog pll. Has anybody done
> this? It's suppose to have the same characteristics of a real analog pll
> including the loop-filter and Vco.
>
> My model is almost done, but I have control problems in some situations.
>
> Help is needed !!!
>
> - Doron Nisenbaum
> Chip Express (Israel) LTD. Haifa , Israel
From: "Bruce Loyer" <bloyer@bad.amd.com>
John,
I have worked with people trying to model an analog PLL in Verilog and
the results were not very good. Two problems come up besides the inherent
problems of doing analog in a digital situation.
One is that a true analog PLL will take quite a while (milliseconds) to
stabilize. You should see this if your doing an accurate simulation. No
one wants to wait a millisecond before beginning the rest of the system
simulating.
Second was that we had to make the timescale very small (much less than
one picosecond) to get good results. This slowed the entire system
simulation down to a crawl. We did not expect that with an event
simulator but it did happen.
This leads one to simulating the PLL separately and then feeding the results
(jitter, frequency wander, etc.) into the Verilog model. If you are going
to do this, you might as well simulate the PLL in spice and get more
accurate results. Good luck.
- Bruce Loyer
AMD
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