( ESNUG 316 Item 2 ) ----------------------------------------------- [4/8/99]
Subject: ( ESNUG 315 #7 ) hdlin_use_cin Works With Verilog But Not VHDL
> I read the post about using the switch hdlin_use_cin = true. Could you
> ask [ Kenny from South Park ] to post an example design that shows a
> post-synthesis failure? I've been teaching people in the Synopsys
> Advanced Verilog classes for the past 2 years to use this switch and to
> add it to their .synopsys_dc.setup file, because of the remarkable
> improvement that this switch causes to the size and speed of arithmetic
> logic designs. ... Looking at Kenny's description, I tried to recreate
> a failure but without success. ...
>
> - Cliff Cummings
> Sunburst Design Beaverton, OR
From: [ Kenny from South Park ]
John,
The "hdl_use_cin" bug is Synopsys "star" id 67812. I filed it under logid
78563 with Synopsys.
It appears to be a VHDL Compiler bug, because it does not exist in the
Verilog Compiler. (I noticed it when I was doing something "funky" with
variables in a VHDL process statment.)
I can e-mail you the test case I sent to Synopsys, but it's pretty involved
VHDL code.
- [ Kenny from South Park ]
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