( ESNUG 313 Item 5 ) ---------------------------------------------- [3/10/99]
Subject: ( ESNUG 311 #4 ) Comparing Verilog Cycle-Based Simulators
> We are looking for a high performance (> 300 cps) Verilog Cycle-based
> simulator. We are evaluating Speedsim but don't have time to evaluate all
> others, especially Cobalt, the Cadence alternative. Our verification
> environment compares responses from our C reference model simulation and
> Verilog models in parallel using IPC and PLI.
>
> Our full chip environment uses lots of PLIs.
>
> Can anyone point out pros and cons and recommend a well proven, high
> performance, easy-to-use Verilog cycle-based simulator ?
>
> - [ The Budweiser Lizard ]
From: [ A Cadence Marketing Guy ]
John,
The gentleman seems to be referring to Cobra (and not Cobalt) here. And
though this might sound like I have my company hat tightly on, it is worth
evaluating. Please keep my name anon. I know that you will have to quote
my co. name because of the nature of my recommendation.
- [ A Cadence Marketing Guy ]
---- ---- ---- ---- ---- ---- ----
From: [ A Synopsys FAE ]
John,
Anything with a lot of PLI is going to be hard to cycle accelerate as most
simulators take a 'generic' approach to the problem in implementing PLI
(not a custom cycle acceleratable approach).
"Bud-wise-ur" didn't specify which product they are using now but there are
a few things that could be done to see where the time is being spent during
simulation (profiling) Especially when using PLI and C models, it's pretty
simple to run something like "gprof" and figure out where the simulation is
taking the most time.
If there is a high amount of intereaction between the C reference model and
Verilog (over IPC) the performance is going to be less than optimal. Faster
machines, multiprocessing, 100Mbs or Gigabit ethernet might help here?
There are some new options/switches in the latest version of Synopsys VCS
that will perform cycle-based optimizations on the Verilog code.
Unfortunately, due to the nature of the PLI, you cannot turn the most
aggressive of these VCS optimizations on.
On the other hand, what I've seen in many cases is changes in verification
methodology can give you a greater speed increase than just throwing a new
set of tools at the problem.
- Are there different levels of abstraction for the "C" model?
- What is the activity across the IPC boundary?
- What level of detail is needed in the interactions between the
"C" environment and Verilog?
- Can the methodology be changed? (Might be a must for using
a hardware approach like Cobalt, Mercury, Axis, etc.)
Lots of things to consider, also knowing the type of design... graphics,
dsp, processor, networking would help with more detailed recommendations.
It's hard to give much more than a "generic" answer given the amount of
info in the posting.
Again, simulator performance is a very design dependent thing. Giving
blanket recommendations on cycles per second is not that useful.
- [ A Synopsys FAE ]
|
|
