( ESNUG 311 Item 3 ) ---------------------------------------------- [2/18/99]
Subject: ( ESNUG 310 #12 ) Convert Verilog To State Machines & Flow Charts
> Does anybody aware of any tool out in the market which can take Verilog
> code as a input and gives FLOW CHART or STATE MACHINES as a result ? I'm
> trying to do a extention of a existing chip where I need to understand
> the implementaion but not much documentaion is available for me.
>
> I know there is a tool which generates code from state machine or flow
> chart (Design Book of Escalade), but I need the other way.
>
> - Gopi Sirineni
> Integrated Device Technology, Inc. San Jose, CA
From: cashley@us.ibm.com ( Carl Ashley )
John,
Summit Design ( www.summit-design.com ) has a tool(s) which take in text
Verilog and produce either block diagrams (standard feature) or flow charts
and state machine diagrams ( additional license ). I have more experience
with the VHDL version of their product. I think generating FSM diagrams is
a bit of "snake oil", but the Summit Text2Graphics feature has recognized
several state machines that I have submitted to it. The Summit tool has
a feature which can be selected to go through the entire design tree (aka
hierarchy) and generate the highest level graphical representation it can
(e.g. FSM, Flowchart, block diagram).
- Carl Ashley
IBM Microelectronics (ASIC Cores Development)
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From: Tsu-Hua Wang <tsuhua@cisco.com>
John,
In reply to ESNUG 310 Item 12, Gopi may want to try free "ciscofsm".
http://www.employees.org/~ciscofsm
Ciscofsm should be superior than many commercial tools.
- Tsu-Hua Wang
Cisco Systems San Jose, CA
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From: Jon McDonald <jmcdonal@gte.net>
Hello John,
Summit Design's Visual HDL will produce Flowcharts and Statemachines from
Verilog or VHDL code.
- Jon McDonald
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From: Scott Evans <scott@NPLab.Com>
John,
I saw a demo from Novas (www.novassoft.com) of a tool they have which is
pretty good at figuring out state machines. Have not used that tool, but
are quite happy with the Debussy software we have from them.
- Scott Evans
NeoParadigm Labs San Jose, CA
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From: Peter Davy <peter_davy@mentorg.com>
Hello John,
Apologies for responding as a vendor but I think we can help. I am a
Technical Marketing Engineer for a product called Renoir. Renoir is an
HDL (Verilog and VHDL) design creation tool. It provides graphical editors
(State Machine, Flow Chart, TruthTable & Block Diagram) as well as design
management capabilities. The part I think you are looking for is the
HDL2Graphics capability which will convert HDL code to appropriate diagrams.
Feel free to find out more from www.renoir.com where you can also download
the product.
- Peter Davy
Mentor Graphics
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From: Oliver Weber <oweber@el.nec.com>
Hi John,
I recommend Visual HDL (for Verilog) from Summit (www.summit-design.com)
This includes also an option called "Verilog to Graphics".
If the original hdl design does not include too many blocks (< 10-15, but
this is relative; depends also on the structuring, number of interconnects
....) within one hierarchy level, then the result is really good.
In the most cases, you don't need to move the blocks/signals by hand.
Also Statemachines and FlowCharts will be produced based on the source HDL
code. Flow Chart tells you not very much, but Statemachine extraction is
good. I have only tried the software for VHDL. But it should produce
nearly the same results as for Verilog.
Another tool, which also generates graphics from HDL, is Renoir from Mentor.
You can download a demo version of this tool from the mentor web page
(http://www.mentor.com/renoir/index.htm) and this demo version is able to
read in HDL and outputs Graphics (which you cannot save in the demo version)
but you will see, the result is not the best. :-)
My evaluation of Renoir, was 5 month ago; possibly they made some changes
in the latest Version.
- Oliver Weber
NEC Electronics (Germany) GmbH
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