( ESNUG 308 Item 12 ) --------------------------------------------- [1/20/99]
From: Brian Boorman <bboorman@harris.com>
Subject: How To Make A Clock Doubler With A FF, An Inverter, & An XOR Gate
There at one time was an App Note from Xilinx on clock doubling. If you
look in an older data book you should be able to find it. (My
interpretation is below.) The caveat is that while frequency is double,
high time pulse width may not be constant as it depends on routing delays.
___________________________________________
| |
| |\ |
| | \ _________ |
O-------------------| |O---| D Q |-----O
| _____ | / | |
|______| | |/ | |
| | | |
| XOR |----o---------|> |
1x CLK _______________| | | | |
|_____| | |_____R___|
| Reset_______|
|___________________________> 2x CLK
Be very careful to ensure that the high pulse meets your device minimum
pulse width requirements. The sum of the Flip-Flop Clock-to-Q delay, route
delay Q-to-Xor, and prop delay through Xor, total of these three will be
your 2xCLK high time.
- Brian C. Boorman
Harris RF Communications Rochester, NY
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