( ESNUG 308 Item 9 ) ---------------------------------------------- [1/20/99]
From: [ Kenny from South Park ]
Subject: Synopsys DW -- Finding What's Available & Forcing DC To Use It
John,
Synopsys DW components are a useful "short cut" for IP. These are little
clusters of wonderful bits of VHDL and Verilog already debugged and ready
to go for the user.
Here's how I do it:
For VHDL RTL code for these various packages, go to the following directory:
$SYNOPSYS/dw/DWXX/src/DWXX_function.vhd
for the entity and
$SYNOPSYS/dw/DWXX/src/DWXX_function_sim.vhd
for the "sim" architecture and "DWXX_function_cfg_sim" configuration.
Compile these into a library called "DWXX" where "XX" is the number of the
DW library (ex DW04).
You will also need the following package in a library call "DWARE" in order
to compile these functions:
$SYNOPSYS/packages/dware/src/DWpackages.vhd
For Verilog, all you have to do is go to:
$SYNOPSYS/dw/DWXX/src_ver/DWXX_function.v
I find these a wonderful way to "force" Synopsys to implement things
the way I want it to.
For example, let's take the following code:
A <= B * C;
By default, Synopsys will create a "Carry-save array synthesis" or "csa"
model of this part, which is a simple, low area, low speed version of a
multiplier -- about the worst possible choice you would want for a
multiplier.
To force Synopsys to use a much faster "Booth-coded Wallace tree" or "wall"
model, you have to do this:
constant R0: resource :=0;
attribute map_to_module of R0: constant is "DW02_mult";
attribute implementation of R0: constant is "wall";
attribute ops of R0: constant is "mul1";
begin
A <= B * C; -- pragma label mul1
Ugly, isn't it? But it works. And it's fully debugged.
- [ Kenny from South Park ]
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