( ESNUG 308 Item 5 ) ---------------------------------------------- [1/20/99]

Subject: (ESNUG 306 #13 307 #2) Routing Layer Preferences Per Pin In DC Libs?

> I found that our Apollo P&R tool supports boolean pin swapping only to fix
> timing violations, but not for routing length reduction.  Bummer.  Now I
> gotta beat on the code developers (some more...)
>
>     - Andy Pagones
>       Motorola Chicago Corporate Research Laboratories     Chicago, IL


From: Michael Rockenhauser <rocky@avanticorp.com>

John,

The issues raised here - that either the router or verification tool are
unable to handle EEQ pins, is rubbish.  Those issues mentioned in this
thread about custom layout not matching the switch-level netlist: those
blocks are often black-boxed and DRC'd separately.

Handling electrical equivalence is a basic capability for both Apollo and
Hercules.  Obviously, these aren't Avant! customers.  If they were in
Milkyway, these issues would not exist.

  - Michael Rockenhauser
    Avant! Corporation                              Derry, NH



 Sign up for the DeepChip newsletter.
Email
 Read what EDA tool users really think.


Feedback About Wiretaps ESNUGs SIGN UP! Downloads Trip Reports Advertise

"Relax. This is a discussion. Anything said here is just one engineer's opinion. Email in your dissenting letter and it'll be published, too."
This Web Site Is Modified Every 2-3 Days
Copyright 1991-2024 John Cooley.  All Rights Reserved.
| Contact John Cooley | Webmaster | Legal | Feedback Form |

   !!!     "It's not a BUG,
  /o o\  /  it's a FEATURE!"
 (  >  )
  \ - / 
  _] [_     (jcooley 1991)