( ESNUG 307 Item 5 ) --------------------------------------------- [12/16/98]
Subject: ( ESNUG 306 #3 ) Bizarre 13% - 41% Area Increase W/ Aspec Libraries
> I'm using Aspec libraries, and Synopsys 1998.02 and 1998.08.
>
> Even though I use no rams in my design, my design team shares a common
> setup script, therefore a "ram.db" is added into everyone's (including my)
> link_library and target_library.
>
> Here's the problem: Although I don't have any rams in my design, the areas
> increase about 15% to 40% if the *unused* Aspec RAMs are linked in!
>
> I submitted this bug to Synopsys two months ago. They re-produced the
> problem but no workarounds for me so far. They talked to Aspec and looked
> over their .lib source and report that it appears to be OK. When I tried
> all three above scenarios using Cascade libraries, I didn't have any area
> problems at all. (The main difference between Aspec libs and Cascade libs
> is that Aspec uses table lookup timing model, Cascade however uses
> piecewise linear model. I don't think this means anything, but it is a
> known difference between the two libs.)
>
> It's been two months. I can't wait any more. Did anyone run into the same
> situation? Any solutions? Thanks.
>
> - Eugene Ko
> Aureal Semiconductor
From: Scott Evans <scott@nplab.com>
My guess is that you are picking up the wire load area attribute from the
ram library and the tool is adding in additional area to account for the
wiring. The area value is probably not specified in any of your other
libraries.
Check the library compiler documentation for more details on the area
attribute for wire_load groups.
Make sure you set your wire load and operating conditions to come from
specific libraries that do not contain this attribute.
- Scott Evans
NeoParadigm Labs San Jose, CA
---- ---- ---- ---- ---- ---- ----
From: eko@Aureal.com (Eugene Ko)
Scott,
Thanks.
There is no wire load in my ram library, only one timing lookup table and
the ram itself in the file.
Synopsys R&D told me that it should be a bug.
- Eugene Ko
Aureal Semiconductor
---- ---- ---- ---- ---- ---- ----
From: William Liao <wliao@vadem.com>
Hi, John,
Do report_area on all variations, then compare the numbers of cells and
nets. You can find them near the end of the reports. If the numbers
differ, then the total area should be different. To find out why they
are different, see the following paragraph.
Also do report_design on all variations. Pay attention to the Wire
Loading Model area of the reports. It should tell you the wire model
Design Compiler is using, and from which library the model is. If each
variation uses a different wire load model, Design Compiler might have
used different versions (1x drive, 2x drive, etc) of the basic cell,
causing changes in design area.
Finally, if nothing else works, do report_cell(find("cell", "*")) on
all variations. This will generate detailed cell reports on your
designs, including the instance name, reference name, source libary,
and most importantly size. In the last row of each report it also
sums up the sizes of all cells. You should be able to figure out
what else changes besides the library.
I hope this is helpful.
- William H. Liao
Vadem
---- ---- ---- ---- ---- ---- ----
From: Jay McDougal <jaym@hpcvcdt.cv.hp.com>
Given that the area increases as you add more rams to the db, this is
probably not your problem. However, it is a possibility and it is easy to
check.
Perhaps the Aspec libraries define some very pessimistic wire load models
and your design is using those during synthesis instead of the ones from
your other library. You can check this by looking at the report_design
output.
- Jay McDougal
Hewlett-Packard
---- ---- ---- ---- ---- ---- ----
From: eko@Aureal.com (Eugene Ko)
Jay and John,
Thank you for help.
There are no wireload models inside Aspec ram, so that wasn't the problem.
I finally got a workaround last night from the Synopsys Support Center.
They said put 'dont_use' on rams. I'll let you know the result after I
test it. Thanks.
- Eugene Ko
Aureal Semiconductor
---- ---- ---- ---- ---- ---- ----
From: eko@Aureal.com (Eugene Ko)
John,
I just verified the workaround from Synopsys R&D/AE. Always set_dont_use on
rams -- doesn't matter if you use them or not. The problem then goes away.
Thank you all for your help.
- Eugene Ko
Aureal Semiconductor
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