( ESNUG 307 Item 4 ) --------------------------------------------- [12/16/98]
Subject: (ESNUG 306 #7) DC Won't Buffer Module Outputs W/ Bottom-Up Approach
> We are using a bottom up synthesis approach for a chip that we are doing
> with LSI. On our critical paths dc is leaving ***A drive parts on the
> outputs when all the cells in the paths up to the output have C and D
> drive. We are using
>
> set_load load_of (lcbg10pv/BUFA/A) * 5.0 all_outputs();
>
> which might be a little weak for nets that are enclosed by a much larger
> wireload model, BUT even at the lowest compile level the last
> incremental delay is the largest in the path because dc won't upgrade
> from an A drive cell at the output! And these are paths that don't meet
> their constraints at the lowest levels! Why won't dc increase the drive
> strength of our output cells?
>
> - Greg Brookshire
> Peracom Cary, NC
From: [ A New Jersey Synopsys AC/FAE ]
John,
I'm an AC/FAE in the New Jersey office. Just out of curiosity, does the
following help at all?
set_max_delay 0.5 -to all_outputs()
(Using 0.5 might be off; use something representative of your flops'
CLK-to-Q.) What I'm wondering is, with a combination of the set_load on
the output and the timing requirement of a fast path from that output,
maybe this will help convince Design Compiler a high-drive flop really
*is* a good idea. :)
Another thing which helps a bottoms-up strategy go a little more smoothly
is a set_load on the input ports of your submodules, if you're not already
doing it. While set_driving_cell tells Design Compiler what is driving
an input port, set_load on an input informs it that it's sharing that drive
ability with other cells/blocks.
- [ A New Jersey Synopsys AC/FAE ]
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