( ESNUG 307 Item 2 ) --------------------------------------------- [12/16/98]
Subject: ( ESNUG 306 #13 ) Put Routing Layer Preferences Per Pin In DC Libs?
> I'm a new Synopsys user. Our cell library has lots of ways to save metal2
> tracks by routing metal1 between adjacent cells.
>
> We'd like Synopsys to choose pin connections based on routability. That
> is, if a cell has a set of boolean equivalent pins but only one can connect
> with metal1, then Synopsys should connect to *that* pin if its target
> connection pin is also metal1-enabled.
>
> Is there a way to specify this in the library??? I'd rather not try to
> tweak delay numbers to make one pin more "attractive" than the others.
> Perhaps there is another clever workaround.
>
> - Andy Pagones
> Motorola Chicago Corporate Research Laboratories Chicago, IL
From: tomd@silogix.com (Tom David)
Hello, John,
I saw this post on ESNUG... I've faced that very same problem before.
Basically I've never found a capability within synopsys to deal with this
issue effectively. Usually this problem is dealt with within the
place&route tool. Your P&R tool must have the capability to understand
equivalent terminals. Therefore it will be able to route to the
electrically eqivalent terminal if it's easier to get to. Of course, this
makes your layout generated netlist different from the netlist extracted
from synopsys. This then causes you to have to turn off equivalent device
cheking in your LVS/DRC tool thus causing untold headaches for the folks
doing custom circuits (like pads and rams etc.). If your custom layout
is very tightly controlled this might not be too big an issue. In my
experience though the analog circuit guys are usually a whole lot more
inflexible than your P&R tool. :-) The other way to potentially resolve
this issue is to route just your digital standard cell block and verify it
against your netlist. Once it's verified clean, extract a netlist from
the layout and use this netlist at the top level. If you do this you
won't have to muck with the LVS/DRC issues...
- Tom David
SiLogiX, LLC
---- ---- ---- ---- ---- ---- ----
From: Andy Pagones-ACIC22 <Andy_Pagones-ACIC22@email.mot.com>
John,
This ESNUG mailing list is very helpful! I'm forwarding copies of ESNUG to
my co-workers so they can sign up, too. Anyway, to follow-up on my question:
I found that our Apollo P&R tool supports boolean pin swapping only to fix
timing violations, but not for routing length reduction. Bummer. Now I
gotta beat on the code developers (some more...)
- Andy Pagones
Motorola Chicago Corporate Research Laboratories Chicago, IL
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