( ESNUG 306 Item 12 ) --------------------------------------------- [12/3/98]
Subject: (ESNUG 305 #4) Use Cadence, Avant!, But NOT DC To Build Clock Trees
> Generally people don't build a clock tree with Synopsys. This is done
> better on the layout synthesis portion of design. You can back annotate
> your design and look for problems/optimizations in Synopsys though.
>
> Avant! has a program called Solar that I hear does well with clock tree
> synthesis.
>
> - Matt Guthaus
> U Michigan
From: paul.sheridan@analog.com (Paul Sheridan)
Hi John,
Regarding using Synopsys for Clock Tree synthesis (ESNUG 305 Item 4), you
might refer readers back to ESNUG 219 Item 1:
> ( ESNUG 219 Item 1 ) ---------------------------------------- [5/26/95]
>
> [ It's a Red Letter Day, Comrades!: This is the first ESNUG contribution
> coming from the other side of the old Berlin Wall! Cool! - John ]
>
> From: OIA@ashtech.msk.su (Orlovsky Igor)
> ........
Orlovsky provided a Synopsys+UNIX-based script which he wrote to generate a
"multi-level balanced tree for any named net in the design". He shows an
example of it working for a clock.
Keep up the great work!
- Paul Sheridan
Analog Devices
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