( ESNUG 305 Item 15 ) --------------------------------------------- [11/18/98]
From: wlentz@ENG.Trimble.COM (Will Lentz)
Subject: Anyone Get Good Results With Power Compiler/DesignPower ? Not Me!
Hi John,
I'm trying to use Power Compiler/DesignPower to reduce power in a design.
All my gated-clocks are done manually, so I'm not using the "elaborate
design -gate_clock" approach. When I try optimizing the design for power,
it only gives a 1-2% decrease in power. From the documentation, I expected
a 10-20% reduction in power...
Has anyone had good results with power optimization using DesignPower?
I'm using the following basic methodology:
1 - compile design normally
2 - write out netlist & timing
3 - simulate design and generate ".dp" or ".saif" file (I've tried both)
4 - read design back in dc_shell
5 - read in ".saif" file (or .dp file)
6 - set_max_dynamic_power 0
7 - compile -inc
On a large design, I "characterize -power" the sub-designs and then try to
optimize them. On small test cases, I just try to optimize from the top
level.
In one case, the power actually went up 1% after the final compile! I can
give my test case or more info if it's needed. Thanks for any help.
- Will Lentz
Trimble
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