( ESNUG 305 Item 12 ) -------------------------------------------- [11/18/98]
Subject: ( ESNUG 304 #3 ) How To Find 3 Unloaded Nets Out Of 300,000 Nets ?
> I have a huge file of set_load commands, obtained from the layout tool.
> The command report_internal_loads can confirm what nets have been assigned
> via the set_load command.
>
> I am looking for a command, or script, to report the nets that have NOT
> been loaded by a set_load command. This is because I want to determine if
> there is any net that escaped the set_load command, and hence the timing
> report may be erroneous.
>
> - Andi Carmon
> Orckit Communications Ltd. Tel Aviv, Israel
From: Jean-Marc Calvez <jean-marc.calvez@st.com>
John,
One possibility is to use the following dc_shell script snippet:
foreach(netname, find(-hier,net)) {
if (get_attribute(-quiet,netname,load) == {}) {
echo "net" netname "not backannotated"
/* or whatever processing */
}
}
Note that the find(-hier,net) is usually very time consuming (alas, I would
like Synopsys spending some time optimizing those "find" and "filter"
functions that are really handy but really slow too), unreasonably so wrt
the time spend in synthesis IMO. Also you may want to redirect the output
to /dev/null to avoid too much clutter in your output file/console.
- Jean-Marc Calvez
STMicroelectronics Grenoble, France
---- ---- ---- ---- ---- ---- ----
From: Jay McDougal <jaym@hpcvcdt.cv.hp.com>
Hi John,
In dc_shell, try the check_design -post_layout command. It will generate
lots of other info about sdf annotations etc., but you can find the
non-annotated nets in the report that is produced.
In pt_shell try the "report_annotated_parasitics -list_not_annotated"
command.
- Jay McDougal
Hewlett-Packard
---- ---- ---- ---- ---- ---- ----
From: jeffb@el.nec.com (Jeff Buckles)
John,
The "-post_layout" option of "check_design" will do this for you, if you're
using 1997.01 or newer.
% man check_design
...
...
-post_layout Checks the design for annotated
information in a Links-to-Layout flow.
This information is annotated on the
design after the design has been placed
and routed by the back-end tool. This
includes delay back-annotation,
resistance back-annotation, capacitance
back-annotation, and PDEF back-
annotation (for example, clusters, cell
locations, and so on). This option lists
designs or instances that have any of
these annotations missing. The
-post_layout option must be used at
least once for a design flow to validate
the back-annotation part of the Links-
to-Layout flow.
One note: depending on how your asic vendor models I/O delays, it may
be OK to have missing net or capacitance annotation on the external
side of I/O buffers.
- Jeff Buckles
NEC Electronics Portland, OR
---- ---- ---- ---- ---- ---- ----
From: Scott Evans <scott@NPLab.Com>
John,
If your design is flat, then you can use "report_net" to get a report which
looks something like:
Attributes:
c - annotated capacitance
r - annotated resistance
Net Fanout Fanin Load Resistance Pins
Attributes
---------------------------------------------------------------------------
B 1 1 7.36 0.00 2
BBOT 1 1 7.36 0.00 2
BBOT_int 1 1 0.28 0.29 2 c, r
BIN0_int[0] 1 1 0.10 0.14 2 c, r
The c,r in the last column shows that a capacitance and resistance have
been annotated to the net. Just delete all the lines that contain c,r and
you are left with those nets that haven't been annotated.
If hierarchical you need to do something like:
report_net find(net -hier"*")
Not terribly efficient but works.
- Scott Evans
NeoParadigm Labs San Jose, CA
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