( ESNUG 305 Item 5 ) --------------------------------------------- [11/18/98]
Subject: Synthesis with Altera RAM Instances
> I have used Altera's "genmem" to create a RAM. The output files were:
>
> 1. syn_ram_8x14_irou.v which contains the Verilog simulation model and
> the RAM instantiation for Synopsys synthesis.
>
> 2. syn_ram_8x14_irou.lib which is to be (somehow) inserted to the
> flex10k-2.db library.
>
> I tried doing a read_lib syn_ram_8x14_irou.lib unsuccesfully. Apparently
> it needs a library header to be able to load. I could not find an app-note
> for this in the Altera web site. Thanks in advance for your help...
>
> - SFCFM Volunteer
From: doron nisenbaum <doron@chipx.co.il>
Hi. I have no experience with Altera rams, but from question I can guess
that the command you should try in order to read the ram is:
update_lib <altera library name> syn_ram_8x14_irou.lib
You can find out the library name using 'list -libraries' command.
- Doron Nisenbaum
Chip Express (Israel) LTD. Haifa, Israel
---- ---- ---- ---- ---- ---- ----
From: "SFCFM Volunteer" <stahr@andix.com>
Thank you! This "update_lib" command is exactly what I needed. Later I
found it in an Altera app note.
- SFCFM Volunteer
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