( ESNUG 304 Item 13 ) -------------------------------------------- [11/12/98]
Subject: (ESNUG 289 #13 303 #11) Test Embedded RAMs W/ My Full SCAN Chain?
> I'm curious if anyone in the chip CAD market can test the embeded RAMs
> through the full scan chain. Are there any EDA products/tools that do
> this? Theoretically, you should be able to accomplish this since there
> are Flip-Flops all around the RAMs, which the scan chain has complete
> control over. Plus, I don't really care how many vectors it takes, as
> long as the process is automagic.
>
> - Victor J. Duvanenko
> Truevision
From: Andrew Hulbert <andrew.hulbert@st.com>
John,
Try looking at the Macrotest feature in Mentor's Fastscan DFT tool. Our DFT
engineer used this feature to test a large percentage of 110 small embedded
RAMs in our lastest design. The small number of RAMs that couldn't be tested
had insufficient test points to allow Macrotest to work. Of the RAMs that
were Macrotested some needed a few additional test points added to the
netlist in the back end flow.
- Andrew Hulbert
STMicroelectronics Limited Bristol, Great Britain
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From: Stephen Sunter <sunter@lvision.com>
John,
A friend of mine forwarded your ESNUG discussion to me, regarding testing of
embedded memories via the scan chain. I'm not a sales person, but the
company that I work for supplies a solution to your problem. LogicVision's
specialty is BIST. We have automation software to insert BIST circuitry at
the RTL level, to test everything via instructions through the JTAG/1149.1
port (or other scan access of your choosing), including:
* memories (embedded or off-chip; SRAM, DRAM, or ROM; single or
multi-port)
* random logic (full or mostly full scan, multi-domain/frequency clocks)
* PLLs (automatically measure loop gain, lock range/time, RMS & pk-pk
jitter)
* I/O and boundary scan logic
* board-level interconnect between ICs with JTAG/1149.1
When testing memories, using the scan access alone can mean very long test
times, does not apply the vectors at-speed, cannot detect certain types of
faults, and is not automatic. BIST allows an at-speed test using vectors
optimized for your specific memory - and it's automatic and diagnostic.
- Steve Sunter
LogicVision, Inc. San Jose, CA
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From: Bejoy Oomman <boomman@genesystest.com>
Hi, John,
We have a product Memory BistCoreTM which is a library of synthesizable,
parameterized, RTL models for implementing Built-In Self-Test of embedded
memories. This can be added to memory behavioral models to achieve fault
coverage without external patterns. If you have an asynchronous memory, it
can also be used as a synchronizing wrapper with BIST capabilities.
- Bejoy G. Oomman
Genesys Testware Fremont, CA
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