( ESNUG 303 Item 4 ) ---------------------------------------------- [11/4/98]
Subject: ( ESNUG 302 #3) Finding Logic0 Cells On Unconnected Scan Ports!!
> Since the scan chains in my design are inserted 'outside' Synopsys, I
> have unconnected (scan out) ports in my design. After a compile run, DC
> connects these unconnected port to logic0. These logic0 cells cause
> problems in the rest of the design flow. I can fix this with a simple
> DC-script that removes these cells, but I was wondering if I can prevent
> the inserting of the logic0's by with some variable or
> attribute???
>
> - Charles E. Klaasen
> Philips Semiconductors Eindhoven, The Netherlands
From: William Liao <wliao@vadem.com>
Hi, John,
There are a few things Charles did not clarify:
1. I don't understand why creating scan chains outside
Synopsys can leave unconnected ports. If the design
has scan capability, Test Compiler should integrate
these scan chains with those it created.
2. Why is the "scan out" ports connected to Logic0? I
think Charles meannt "scan in" ports. Otherwise, isn't
bus contention a problem?
3. Exactly what problems is Logic0 causing? It's possible
that the problems he has isn't caused by Logic0. I have
encountered a few situations like that.
Until I have more info, I am not sure what else to say except that scan out
porst connected to Logic0 will probably cause contention problems.
- William Liao
Vadem
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From: "Charles Klaasen" <klaasen@natlab.research.philips.com
Hi, John,
Let me clarify some things regarding my logic0's. In our design, we have
a number of in- and output ports that are unconnected: the scan in- and
outputs. OUTSIDE ANY SYNOPSYS TOOLS, these ports are connected to some
newly inserted scan FFs. Before that, that is witin DC, our design does
NOT contain any scan FFs. So that leaves us in DC with unconnected
output ports that DC connects to a logic0 as soon as we start any form
of compile run.
If you set:
compile_preserve_subdesign_interfaces = true
you can prevent DC from breaking up your (scan) buses and inserting
logic0's at the top-level. It will leave the buses untouched
and pushes the logic0's one level down in the hierachy.
With a script, I can check for logic0's in the design and remove them. But
it would be much nicer, if I can prevent DC from creating the logic0's in
the first place. Does anyone have any clues???
- Charles E. Klaasen
Philips Semiconductors Eindhoven, The Netherlands
---- ---- ---- ---- ---- ---- ----
From: William Liao <wliao@vadem.com>
Hi, John,
I think I understand the problem now. Let me repeat it, just to be sure.
1. A design has regular FFs and unconnected output ports.
2. Outside Synopsys, regular FFs are replaced with scan FFs and the
unconnected output ports are used as scan out ports.
3. But if compiles are done between steps 1 & 2, Synopsys connects the
unconnected port to Logic0. This is undesirable.
If I am right, then do this:
set_unconnected [unconnected ports]
to solve your problem. It worked on my test case.
- William Liao
Vadem
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