( ESNUG 303 Item 3 ) ---------------------------------------------- [11/4/98]
Subject: ( ESNUG 302 #9 ) To Users: Is VERA A Good Tool For Verification ?
> I am looking for lessons learned from someone who has used VERA in the past.
> Our full-chip Verification environment has Diag that issues commands to the
> HW Abstract Layer which spawns Verilog simulation. The Verilog side then
> forks, and execvp to execute a child process to run C simulation of C
> Reference models.
>
> During the course of C simulation, stimulus and responses around each
> module are envelope-captured. The stimulus are sent to an IPC (Interprocess
> Communication) FIFO to be applied to the Verilog counterpart. The responses
> are sent to another IPC FIFO to be compared to that of the Verilog
> counterpart. The Verilog and C sides are run in parallel and handshake thru
> semaphore and shared memory.
>
> I have two questions of which answers would help us in evaluating the tool.
> First, what is your detailed lesson you learn from using VERA in your
> environment. Any caveat and pitfall of the tool contrary to mktg claim ?
> How does VERA stack up against Specman ?
>
> Second, does anyone have a similar environment as ours and use VERA as a
> cosimulator between C and Verilog sides successfully ? If yes, is there any
> catch ? How are its RPC (Remote Procedural Call) and IPC ? Please keep
> me anonymous because we're looking into a possible purchase of VERA.
>
> - [ Curious Minds ]
From: Rudolf Usselmann <rudi@logic1.com>
John,
The interesting environment that [ Curious Minds ] built allows its
verification team to generate transactions, determine on the fly if they
are correct, and keep the golden and Verilog models in sync. In essence,
they've built a self-checking environment. This environment, combining
Verilog and C, supports some of the capabilities that would be available
with less effort, and in more general ways, in VERA - which is good
news, in that the verification philosphy is alligned.
Apparently the first-level interest is in how VERA would help link all
this C and Verilog, and VERA can do that and more. In regards to the
IPC, VERA allows to make both blocking and non-blocking calls from C to
Vera/Verilog, and vice-versa, and allows any number of cooperating C and
Vera/Verilog processes (in case they also want to distribute the
simulation). In those calls one can pass arguments back and forth too.
To use Vera's IPC, one those not need to know one iota of IPC or PLI:
there's just half a dozen vanilla C routines the user interacts with.
Very simple to use.
However, VERA can do more than that in the direction of a self-checking
environment. Curious Minds have created a very elaborate synchronization
and data exchange mechanism to verify that the actual and predicted
results match. VERA fits well within that approach, and would simplify
the creation of additional transactors, with more flexibility and
varying granularity levels. Some of the finer-grain transactors can
catch many corner cases which are harder to handle with the full-fledged
model that looks only at the boundary. Also, they are easier to write,
and the checkers/tasks which are developed for the module-level tests
can be re-used at system level test.
Beyond that, of course, there are all the other VERA capabilities in
coverage, stimulus generation, floating expects, etc. Finally, the tight
integration of VERA with Flex Models and Eagle allows system-level
verification completely beyond the reach of competing products.
Please also see my VERA write-up in ESNUG 296.
- Rudolf Usselmann, Consultant
Logic One, Inc.
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