( ESNUG 302 Item 4 ) --------------------------------------------- [10/21/98]
Subject: ( ESNUG 300 #5 301 #7 ) Experiences, Scripts, & Benchmarks w/ DC'98
From: Jason Surprise <jmsurpri@ichips.intel.com>
> I just read your recent ESNUG post regarding your findings with DC98.
> Good post. However, I have some concerns with the section of the report
> which talks about set_input_delays on clocks.
>
> In the example that you showed, you are applying a negative delay on the
> clock using set_input_delay -0.82. This, in essence, is changing the
> waveform of the clock, correct. So, your waveform has been changed as
> follows:
>
>
> +--------+ +--------+
> | | | |
> | | | | Before
> | | | |
> --------+ +---------+ +-------
> 0 5 10 15
>
>
> +--------+ +--------+
> | | | |
> | | | | After
> | | | |
> ------+ +---------+ +-------
> -0.82 4.18 9.18
>
>
> So you've just shifted the clock back by 0.82. Looking at your timing
> report, I don't see this shift happening, all I see if the .82 taken
> from the originating clock, but not taken away from the sampled clock.
> Seems like a bug to me.
>
>
> Point Incr Path
> -----------------------------------------------------------
> clock clk (rise edge) 0.00 0.00
> clock network delay (propagated) -0.82 -0.82
> q_reg/CK (DFF) 0.00 -0.82 r
> q_reg/D (DFF) 1.29 0.47 r
> U9/Y (BUFX1) 0.08 0.55 f
> q (out) 0.00 0.55 f
> data arrival time 0.55
>
> clock clk (rise edge) 10.00 10.00
> clock network delay (propagated) 0.00 10.00 <-- This should
> output external delay -8.00 2.00 read -0.82 !
> data required time 2.00
> -----------------------------------------------------------
> data required time 2.00
> data arrival time -0.55
> -----------------------------------------------------------
> slack (MET) 1.45
>
>
> What do you think?
>
> - Jason Surprise
> Intel Hillsboro, OR
From: sgolson@trilobyte.com (Steve Golson)
Jason,
Not exactly. What I did was this:
create_clock -period 10 find(port,CLK)
set_clock_skew -propagated find(clock,CLK)
set_input_delay -3.82 -clock CLK find(port,CLK)
So I started with an ideal clock that rises at 0 and falls at 5. Then
I shifted the clock back by 3.82. However this is a *propagated* clock,
which means all the real back-annotated delays on the clock network will
be used. In my example the delay from the CLK input to the source flop clock
pin has 3.00 delay for a total delay of -0.82 (which is what the timing
report shows). The delay from the CLK input to the destination flop will be
different because of skew in the clock network.
I should have picked a better example that had a destination flop rather
than an output.
- Steve Golson
Trilobyte Systems
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