( ESNUG 301 Item 5 ) --------------------------------------------- [10/15/98]
From: ( Greg Brookshire ) gbrookshire@peracom.com
Subject: Why Does Synopsys Seem To Give Us Inconsistant Timing Reports?
Hi, John,
We are building a 500k gate chip with LSI. When we do top level timing
reports we see may clk-to-q times of more than 3ns for nets with only a
fanout of 2. We are using the "enclosed" mode for wireloading, but these
nets are contained within small blocks. When we time the enclosing block
the exact same nets have delays less than 0.5ns. (?)
Startpoint: core/atm/at_learn0/learn_fsm/sa_rd_req_reg
(rising edge-triggered flip-flop clocked by pad/clk)
Endpoint: core/ebm/reqq/flow_fifo_reg[0][2]
(rising edge-triggered flip-flop clocked by pad/clk)
Path Group: pad/clk
Path Type: max
Point Fanout Incr Path
----------------------------------------------------------------------
clock pad/clk (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
core/atm/at_learn0/ln_fsm/sa_rd_req_reg/CP (FD2QC) 0.00 0.00 r
core/atm/at_learn0/ln_fsm/sa_rd_req_reg/Q (FD2QC) 3.69 3.69 f
core/atm/at_learn0/ln_fsm/sa_rd_req (net) 2 0.00 3.69 f
core/atm/at_learn0/ln_fsm/sa_rd_req (at_learning_fsm_1) 0.00 3.69 f
core/atm/at_learn0/sa_rd_req (net) 0.00 3.69 f
core/atm/at_learn0/sa_rd_req (at_learning_1) 0.00 3.69 f
core/atm/sa0_rd_req (net) 0.00 3.69 f
core/atm/mem_sched/sa0_rd_req (at_mem_sched) 0.00 3.69 f
core/atm/mem_sched/sa0_rd_req (net) 0.00 3.69 f
core/atm/mem_sched/U325/Z (N1D) 0.10 3.79 r
core/atm/mem_sched/n479 (net) 4 0.00 3.79 r
core/atm/mem_sched/U572/Z (ND2C) 0.15 3.93 f
core/atm/mem_sched/n454 (net) 2 0.00 3.93 f
core/atm/mem_sched/U374/Z (ND2B) 0.09 4.02 r
core/atm/mem_sched/n561 (net) 1 0.00 4.02 r
core/atm/mem_sched/U574/Z (ND2C) 0.15 4.17 f
core/atm/mem_sched/n467 (net) 2 0.00 4.17 f
core/atm/mem_sched/U567/Z (NR2C) 0.11 4.28 r
core/atm/mem_sched/n466 (net) 1 0.00 4.28 r
core/atm/mem_sched/U321/Z (NR2C) 0.10 4.38 f
core/atm/mem_sched/n328 (net) 1 0.00 4.38 f
core/atm/mem_sched/U378/Z (AO4C) 0.22 4.60 r
Can anyone explain the large difference in clk-to-Q times?
- Greg Brookshire
Peracom Cary, NC
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