( ESNUG 299 Item 8 ) ---------------------------------------------- [9/21/98]
Subject: (ESNUG 296 #9 297 #10) Cadence's PB-OPT Trounces reoptimize_design
> With regard to Cadence's PB-OPT, I implemented this tool flow (in a former
> life) and used it on very high performance designs. The results seemed to
> match Cadence's claims and this option enabled me to achieve a one-pass,
> timing-convergent, design flow from RTL->layout. This additional feature
> allowed me to replace my previous methodology, which was to iterate
> (sometimes > 15 times) through Design Compiler's reoptimize_design and
> Cell3/Silicon Ensemble's ECO place and route.
>
> - Brian Arnold
> Fusion Networks Corp. Longmont, CO
From: Chakki Kavoori [chakki@Aureal.com]
To: Brian Arnold <briana@SiTera.com>
Hi Brian
I read your response on the ESNUG post regarding generating gcf files
from Synopsys constraints file. I was just curious if you used the sdf
constraints file, or was it some other report that Synopsys generated?
(could you be more specific on the command, too?)
We're just starting to migrate to the Cadence recommended Timing Driven
Flow (including PB-Opt) - one of the things I find missing from PB-Opt is
an equivalent of the Synopsys "don't touch" command -- where I know better
than to resize some of the elements because I have them "spiced". Did you
face any such issues/problems?
Were you using Silicon Ensemble (SE) in a flat mode or did you do any
hierarchies -- and if you used hierarchies -- did you use Design Planner (DP)
as the floor planner? I'm interested in finding out about your experiences.
- Chakki Kavoori
Sr. Design Engineer,
Aureal Semiconductor Fremont, CA
---- ---- ---- ---- ---- ---- ----
[ Editor's Note: Before Brian answers these questions, I thought I'd
provide a set of definitions for the Synopsys users to better understand
the Cadence tools being discussed.
DP - Design Planner. DP typically refers to LDP.
LDP - Logical Design Planner. Reads in Verilog and produces groups
and a pin placement that assists QP in doing a better job. It also
generates custom wire load models for you. This package is priced
in the "arm or leg" realm.
PDP - Physical Design Planner. Incorporates the functionality of LDP
and provides an interface for you into SE (Silicon Ensemble), the CCT
router (Cooper & Chan Technologies) as well as Cadence's back end
analysis tools (I think). This package is priced in the "arm & leg
plus your first born child" realm.
SE - Silicon Ensemble. It is the replacement for Cell3 and includes
QP (Quadratic Place) and Wroute (Warp Router). PBOPT (Placement Based
Optimization) is an option to SE as is CTGEN (Clock Tree Generation).
This package is priced in the "arm & leg plus your first born child
plus the Devil gets your soul" realm.
Hope this makes the following reply more understandable now. - John ]
---- ---- ---- ---- ---- ---- ----
From: Brian Arnold <briana@SiTera.com>
To: Chakki Kavoori [chakki@Aureal.com]
Chakki,
The great thing about using the GCF format is you do not need an SDF
file. The GCF format accomplishes the same result as does the Synopsys
constraint file. GCF defines clocks, input and output delays, input
slopes and output loading, then the internal timing engine (Pearl in the
case of PBOPT) performs the appropriate calculations between all timing
begin/end points, which is comparable to Design Compiler calculating
timing arcs during a compile. However, Pearl/PBOPT is also able to
analyze the routing of the wires and get a very good idea of the load on
each wire and appropriately size/split/move_cells on each net. The
default mode for PBOPT is to generate an RSPF file from a global route,
however, I found this to not be as accurate as I needed. Therefore, I
modified the PBOPT flow so it used an RSPF file from a first pass timing
driven P&R run. Therefore, the layout data seen by PBOPT was as
realistic as possible. The entire tool flow from HDL->GDS does become
rather complex when you have to maintain consistency between the HDL and
Synopsys db files and schematics and artwork layout, but it is manageable
just as long as the PBOPT Verilog writer produces the results you need.
In order to reduce the amount of complexity seen by the users, I wrapped
this tool flow (from HDL->Synthesis->floorplanning->P&R->GDS) into a GUI
that allowed a designer to "easily" navigate their block through all the
steps. I didn't think of this idea (kudos to Steve Rich), I just
implemented my own version (thanks for the toolkit Dave Clark). When you
have a lot of people using a complex tool flow, this is a great path to
take. The amount of up front work, really pays off in the amount of
day-to-day support you have to provide and the increase in productivity
seen by the designers.
Getting back to your SDF question, I do not personally like to use SDF
as it has three main problems:
1) The files take a long time to create/read
2) The file size is huge for large designs
3) SDF misses paths and does not provide complete coverage, which leads
to problems for timing driven placement
I know most of the Synopsys constraint commands has an equivalent in the
GCF realm, but I don't know about dont_touch, I'm sure it does but I
don't have my GCF spec handy, call your local PBOPT AE and ask him for a
GCF spec. I don't have an example of a GCF file for you or I would send
it. As I did just change jobs I couldn't take any of this with me, bummer.
No, I didn't use DP as the floorplanner, I wrote my own that helped designers
create a custom floorplan on a block-by-block basis. My wrapper around the
Silicon Ensemble (SE) flow extracted the floorplan information and fed
it into SE during a floorplanning step. This allowed a designer much
tighter control over what their block looked like. With this capability
they could insert things into the floorplan like pre-placed wires,
preplaced cells, blockages, groups and regions very easily. The
composed blocks were then connected together at a higher level and
eventually routed with the full chip. LDP didn't help me out at all,
mostly because of the type of designs that I ran through SE. However,
for very large designs I can see how LDP would be beneficial as it has
capabilities to automatically determine pin placements, create groups
and run through QP, and I was told that PDP is a good interface if you
continue on and use CCT for your top level route.
The designs I fed into SE were flat, but in general, the designs were
very hierarchical. The process I used that generates DEF flattens the
hierarchy to one level. However, those blocks that did utilize PBOPT
were flattened in synthesis (which may have alleviated a lot of problems
for me, I don't know). Therefore, I'm not sure how good of a job the
PBOPT Verilog writer does at generating hierarchical Verilog as I never
needed to test it out.
- Brian Arnold
SiTera Incorporated Longmont, CO
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