( ESNUG 292 Item 9 ) ----------------------------------------------- [6/4/98]
From: Keith Calder <keith.calder@gecm.com>
Subject: DC 98.02 Makes Crappy Initial DesignWare Selections
John,
Design Compiler 98.02 seems to have a problem when selecting arithmetic
components to meet specified timing constraints.
After some experimentation, I have come to the conclusion that the part is
selected on the basis that subsequent optimizations will be able to reduce
worst case delays by a certain, predefined, amount. Unfortunately, this
predefined value appears to be incorrect and on subsequent optimizations the
DesignWare element will be optimized but not sufficiently to meet the timing
requirements.
There can be faster implementations in the Standard or Foundation libraries
but these will not be selected.
I have got around this problem by carrying out an initial low effort
synthesis with faster clock constraints, which selects the required
DesignWare implementation. On then setting the clock constraints to the
desired value a subsequent compilation will then give a design with no
timing violations.
Is there a better way other than selecting individual implementations
within the HDL?
- Keith Calder
GECM
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