( ESNUG 289 Item 11 ) ---------------------------------------------- [5/13/98]
From: Magnus Jacobsson <Magnus.Jacobsson@era.ericsson.se>
Subject: My Life Is A Living HELL Because Xilinx Has No Damn SCAN FF's !
Hi John,
We're working on a full-scan design where we're using the scan flip-flops not
only for test purposes, but also as a part of the functionality. In order
to verify parts of the design together with external hardware before we go
to silicon we're developing a prototype board with a Xilinx XC40125 FPGA
device.
A problem we have encountered is that we can't use insert_scan because there
are no scan flip-flops in the Xilinx library. Instead we have synthesised
the design to an ASIC library (lsi10k), performed scan insertion and then
reoptimized towards the Xilinx library. This works but gives quite some
area overhead which is very unfortunate since we're having problems fitting
it into the device. My question is if somebody have a better way of doing
this. Neither Synopsys or Xilinx have come up with a better solution.
People I've talked to have given me some suggestions:
1. Add a scan flip-flop to the Xilinx library. How do I do this?
2. Force Synopsys to create a mux in front of a normal flip-flop instead
of trying to use a muxed flip-flop from the library. A rumour says
that an earlier version of Synopsys did this and that it is possible
to force it into this "old mode". How do I do this?
3. Create a script that "manually" inserts the muxes and add appropriate
attributes in order for insert-scan to work. What attributes are
that and how should they be set?
If someone has done this before or have any other ideas on how to do it I'd
appreciate if you could share them on ESNUG.
- Magnus Jacobsson
Ericsson Radio Systems Kista, Sweden
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