( ESNUG 289 Item 6 ) ----------------------------------------------- [5/13/98]
Subject: ( ESNUG 288 #12 ) Want Testbench With Both Internal & Boundry Scan
> One of the feature I particularly appreciate is Test Compiler that gives
> me the possibility of synthesizing internal scan chains and boundary scan
> circuitry, compliant to 1149.1 JTAG standards. .... To be honest I still
> haven't obtained a test-bench that gives stimuli to the TAP pins: TCK,
> TMS, TRST and TDI, but only to the inputs of the scan chains. For the
> JTAG output TDO the testbench asserts that the value desired is 'Z' from
> the beginning to the end.
>
> - Davide Falchieri
> Bologna University Bologna, Italy
From: "Geoff Jones" <gjones@atl.com>
I've used the Synopsys generated boundary scan logic and it does seem to
work. One problem was that it insisted on routing 'observe only' input
signals through the capture boundary scan cell. (i.e The signal from the
pad was routed to the boundary scan register cell and then on to the core
instead of just branching off from a direct route from pad to core.) This
could have caused long delays on input signals if the boundary scan cells
were not placed in a good position.
The version of the Synopsys tools that I used did not make any test vectors
for the boundary scan circuit. I ended up writing a program in C++ that
parses the report file to create a model of the JTAG logic that can be
driven with commands like 'read idcode' and 'load_instruction extest'. This
made an ASCII file that I could use in a testbench to drive the gate-level
sim. It also predicted the output of TDO whenever it could. It also writes
out a BSDL description of the chip. If you really want to try some
home-made software e-mail me and I'll send you the files. (Works on HPUX
g++ and PC Visual C++).
- Geoff Jones
ATL Ultrasound
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