( ESNUG 289 Item 4 ) ----------------------------------------------- [5/13/98]
Subject: ( ESNUG 288 #10 ) Escalade vs. Summit and Mentor Renoir vs. Speed
> I was wondering if anyone else is looking at Escalade's Design Book
> as an alternative to Summit and Mentor's Renoir?
From: Geir Harris Hedemark <geirhe@hridil.ifi.uio.no>
I have tried the release of Renoir (on NT) Mentor distributed last fall. It
had quite a few bugs, and I was not impressed after having read the four
color glossies. The HPUX version was even less streamlined than the NT one.
I have not been able to test the latest (C.1) release yet, but I strongly
suspect things are better now.
Vicious tongues say that Renoir is a blueprint of Summit's graphical entry
tool. I have not tried Summit's tools myself, and cannot say whether this
is true.
But over to graphical entry: I quickly found that graphical entry was not
the thing for me. I spent way too much time moving graphical thingamabobs
around on the screen relative to the time I spent actually doing something.
I think a good VHDL programmer is able to write program code much faster
(and visualize it in his own head) than a graphical entry tool can show you,
provided he has got a good editor that helps him write VHDL.
However, I will be using Renoir the "other way around", for making
documentation. Once I have written and tested my VHDL code, I am going to
stuff the VHDL code into Renoir to make Pretty Pictures of it. This will
enable people that are not fluent in VHDL to double-check the functional
correctness of my code. I think that will be a great bonus, well worth any
licensing fees (within reason). It will also ensure (providing Mentor has
done their job) that the documentation corresponds to the implementation.
Stuffing VHDL code into Renoir isn't a time-consuming task, either, and I
won't wreck my lower hand tendons doing it.
Note that I am an emacs/unix diehard and a quite fast typist. I use lynx
when I surfe the web, and I don't like using a mouse more than absolutely
necessary. YMMV.
- Geir Harris Hedemark
University of Oslo, Norway
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From: zuk@ll.mit.edu (W. S. Zuk)
We have used Speed Electronic's speedchart since 1995 with great success.
We used it for entire, top down chip design, not just "state machines".
Unfortunately, Speed Electronic went out of business last August.
Ironically, Mentor bought the assets of Speed and hired some of the staff.
IMO, the product Mentor should have copied is Speed. In fact, since they
now own the Speed source code, IMO they should just add a button to their
Renoir GUI to enable the Speed tool, or better yet, just re-sell the Speed
product the same way they re-sell interconnectix and Model Tech.
I agree wholeheartedly that these "MS Windows" look & feel user interfaces
are so weak and un-automated for graphical drawing so as to be certainly
frustrating and nearly useless. A good, professional level graphical
entry tool designed for someone running the tool many hours a day (along
the lines of old fashioned unix-based schematic tools such as Viewlogic's
viewdraw) makes a huge difference in productivity. That is what Speed
offered. (Actually, I consider speedchart a generation ahead of viewdraw
in terms of automated drawing functions). All the other HDL graphic
offerings that I know of are "me too's" w/ a weak and overly cumbersome
drawing package.
I think it's inevitable as HDL designs get handed around among different
designers and get larger and larger that a good graphical tool will help
productivity and maintenance.
IMO the "old" speedchart tool had it right & allowed top down design entry
graphically.
- Bill Zuk
MIT
P.S. -- Is there life after death? I see there's an article about Speedchart
in the May 1998 issue of Integrated System Design magazine, pg38-48.
---- ---- ---- ---- ---- ---- ----
From: Mike Treseler <tres@tc.fluke.com>
I have evaluated several and have so far found nothing more efficient than a
good text editor and synthesis tools. I used to believe that I needed a
schematic view of the top level, but changed my mind after trying to do it.
My experience was that getting the "wires" right on a graphical view tried my
patience more than getting a concise text version of the same thing. I was
also surprised by how many gates and flops could spew from a few lines of
code.
I found that the "view schematic" function of the synthesis tool gave me all
the information I really needed to know about what was going on with the
primitives. With a graphical top level, you get a minimum of one block
diagram sheet then one other page describing each block. With text-only the
minimum is one page of text. So now if I need a block diagram, I draw it
in my notebook.
To answer your question, my favorite graphical tool and the easiest to
evaluate is Renoir. You can downloaded from mentor's website and get a
temporary key by email with no hassle. But get out your wallet if you want
to buy it.
The best deal for the money is a pencil and paper.
The second best deal for the money is CompLib (e-mail riitta@hantro.com)
- Mike Treseler
Fluke Networks Division Everett, WA
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From: Geir Harris Hedemark <geirhe@hridil.ifi.uio.no>
Let us be fair. I don't think Mentor targets professional asic designers
with Renoir. I think they are targeting people who make an fpga now and
then. These people won't use the tool enough to be able to learn an
efficient graphical entry user interface (the emacs interface holy war
springs to mind here), and for them, Windows look and feel is just what the
doctor ordered.
- Geir Harris Hedemark
University of Oslo, Norway
---- ---- ---- ---- ---- ---- ----
> But over to graphical entry: I quickly found that graphical entry was not
> the thing for me. I spent way too much time moving graphical thingumabobs
> around on the screen relative to the time I spent actually doing something.
From: T Wang <tsuhua@cisco.com>
I totally agree with the above comment. Especially, try to draw a finite
state machine with 15 states, 45 transitions and 75 conditions. I'll spend
95% of my time to make my fsm look pretty and 3% of time to worry about my
fsm design.
I have discussed this matter with many experienced CAD & hardware designers.
Our conclusion is that they are not that useful.
However, Text2Graphics is very very powerful. We found TWO BUGs by examing
the fsm bubble diagram (no simulation). I call this "visual verification".
Also, designers bring their fsm bubble diagram for the code reviews.
In my opinion, the best bubble diagram drawing tool is AT&T's "dot" or
related products. And, it is FREE. To learn how we found two bugs, please
consult the IVC'98 paper:
http://www.employees.org/~ciscofsm
http://www.research.att.com/sw/tools/graphviz
BTW, the paper shows, thanks to dot, the 15 states, 45 transitions and 75
conditions bubble diagram.
- Tsu-Hua Wang
Cisco Systems
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From: Adam Atherton <atherton@syr.lmco.com>
I have used VisualHDL from Summit extensively in an FPGA design process and
found the block diagram schematic entry to be really good. I have never
used any others so I don't have much to compare it against though. The block
diagrams are easier to understand, and trace signals in, and the code that
was produced was extremely close to how I would have written it using a text
editor. For small designs, a text editor may have been faster, but in terms
of large designs, I found it invaluable. Also, as another incidental bonus,
you should have heard my program engineer raving about the quality of the
diagrams compared to my usual atrocious handwriting.
- Adam Atherton
Lockheed Martin Syracuse, NY
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From: vincent@dtcs09.kodak.com (John Vincent)
In considering graphical HDL entry tools, you may also wish to consider
Escalade's Design Book product. We have looked at it a bit and seems to
have some advantages over other competitors in some areas. It really
depends on your objectives for the tools. We decided we needed to formally
assess users needs to decide which tool is best suited to our needs.
One thing I liked about Escalade was their ModuleWare library of
parameterized functions. These are nice for datatpath design and not
restricted to LPM functions. I consider these to be especially valuable to
new HDL designers. It was actually in looking for this capability that
learned of Escalade.
We have looked at both tools a little a while back. Escalade seemed to
be easier to use and more intuitive. It had some convenience features
in the state machine editor which Summit did not. We also had a state
diagram in Summit which produced code which would not synthesize. On
the other hand. Summit had better HDL import capability and some of
the experienced VHDL designers preferred the way Summit used libraries.
We have one seat of each currently and are going through a formal
assessment of them along with Renoir, looking at their capabilities
against user needs.
Generally, experienced VHDL users are not very receptive to the use of
graphical tools, except perhaps for doing complex state machine design.
Most will concede that it is a lot easier to share information if it
graphical than textual. Personally. I am for whatever one feels to be
the most effective. I advocate a mixed approach, with **overall**
productivity (which includes documentation and reuse) being the objective.
I consider HDLs as a means to an end, not an end in themselves. The ability
to easily switch between graphics and text or between languages is IMHO
the goal.
- John Vincent
Eastman Kodak Company Rochester, New York
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> Let us be fair. I don't think Mentor targets professional asic
> designers with Renoir.
From: johne@vcd.hp.com (John Eaton)
Well they have certainly priced it for the professional asic designer.
I am a firm believer that for some areas of an asic that a picture is worth
a thousand words. So I have been looking for a good graphical entry tool but
have not been overly impressed with any of the current offerings.
You can do block diagram entry with any schematic capture package that
has verilog, vhdl or edif netlist output. I have to use schematic capture
anyway when I lay out test and product boards and it makes sense to use
the same system to create the top level of the chip.
So do they build their block diagram editors around existing schematic
systems that someone might already use? No they create a whole new tool
that you have to buy and learn.
Schematic capture packages at least let you define the shape of your symbols.
Some of these "block" diagram editors seem to think that any shape as long
as it's rectangular is fine. I would like to see these guys lay down a sheet
full of synopsys designware primitives using theirs tools that actually is
understandable.
ASIC designers are suffering from tool overload. We do not need more tools
that take more time to install and learn than they save.
- John Eaton
Hewlett-Packard
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