( ESNUG 288 Item 12 ) ---------------------------------------------- [5/7/98]
From: Davide Falchieri <davide.falchieri@bo.infn.it>
Subject: Can't Obtain A Testbench That Has Both Internal & Boundry Scan
Hello,
I have just begun by now using Synopsys tools and I have found they are
more powerful than Cadence for every step of the design flow. One of the
feature I particularly appreciate is Test Compiler that gives me the
possibility of synthesizing internal scan chains and boundary scan
circuitry, compliant to 1149.1 JTAG standards. An other remarkable tool
is the ATPG tool that allows creating very effective test-benchs in few
hours: my problem is that I can't automatically obtain a test-bench that
takes into account for both internal and boundary scan. To be honest I
still haven't obtained a test-bench that gives stimuli to the TAP pins: TCK,
TMS, TRST and TDI, but only to the inputs of the scan chains. For the JTAG
output TDO the testbench asserts that the value desired is 'Z' from the
beginning to the end.
Have I to perform some manual modification of the schematic (that's
really not so simple under Synopsys) ? Or isn't it possible at all ?
If there is some Synopsys Test Compiler users I would be glad to talk
with them for exchanging opinions and ideas.
- Davide Falchieri
Bologna University Bologna, Italy
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