( ESNUG 286 Item 5 ) ---------------------------------------------- [4/13/98]
Subject: ( ESNUG 282 #8 ) Library Compiler Won't Take Discharge Cells
> I have a problem/challenge - how to "feed" Library Compiler with discharge
> cells? As it was proposed in the course -- the general direction is to
> define it as an ITS module. I've been searching in the openbook
> ("Synopsys On-Line Docs") for an example of discharge cells but I found
> none.
>
> I would appriciate if someone could send me an example of ITS format
> with the required timing arcs (I mean the names/kinds of arcs -- not the
> numbers) for a discharge cell. Here is an example of a typical circuit:
>
> +---o NOUT
> |
> |
> EN---||
> |
> |---------+
> A---|| |
> | B---||
> | |
> | |
> | C---||
> | |
> | |
> \/ \/
>
> Let's say that the EN input is clock or "something & clock"
>
> - Eran Vodevoz
> Analog Devices Herzlia, Israel
From: Eran Vodevoz <eran.vodevoz@analog.com>
John,
I just wanted to follow-up on my problem. Here's an example I got from
Synopsys on how to model a Discharge Cell in Library Compiler:
library(Lib1) {
default_inout_pin_cap : 1.0;
default_inout_pin_fall_res : 0.0;
default_inout_pin_rise_res : 0.0;
default_input_pin_cap : 1.0;
default_intrinsic_fall : 1.0;
default_intrinsic_rise : 1.0;
default_output_pin_cap : 0.0;
default_output_pin_fall_res : 0.0;
default_output_pin_rise_res : 0.0;
default_slope_fall : 0.0;
default_slope_rise : 0.0;
default_fanout_load : 1.0;
k_process_drive_fall : 1.0;
k_process_drive_rise : 1.0;
k_process_intrinsic_fall : 1.0;
k_process_intrinsic_rise : 1.0;
k_process_pin_cap : 0.0;
k_process_slope_fall : 1.0;
k_process_slope_rise : 1.0;
k_process_wire_cap : 0.0;
k_process_wire_res : 1.0;
k_temp_drive_fall : 0.0037;
k_temp_drive_rise : 0.0037;
k_temp_intrinsic_fall : 0.0037;
k_temp_intrinsic_rise : 0.0037;
k_temp_pin_cap : 0.0;
k_temp_slope_fall : 0.0;
k_temp_slope_rise : 0.0;
k_temp_wire_cap : 0.0;
k_temp_wire_res : 0.0;
k_volt_drive_fall : -0.26;
k_volt_drive_rise : -0.26;
k_volt_intrinsic_fall : -0.26;
k_volt_intrinsic_rise : -0.26;
k_volt_pin_cap : 0.0;
k_volt_slope_fall : 0.0;
k_volt_slope_rise : 0.0;
k_volt_wire_cap : 0.0;
k_volt_wire_res : 0.0;
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1uA";
pulling_resistance_unit : "1kohm";
capacitive_load_unit (0.1,ff);
nom_process : 1.0;
nom_temperature : 25.0;
nom_voltage : 5.0;
cell(discharge) {
area : 1;
interface_timing = TRUE;
pin(A) {
direction : input;
capacitance : 1;
}
pin(B) {
direction : input;
capacitance : 1;
}
pin(C) {
direction : input;
capacitance : 1;
}
pin(EN) {
direction : input;
capacitance : 1;
clock = true;
}
pin(NOUT) {
direction : output;
timing() {
timing_sense : negative_unate;
when : "A&!(B & C)";
sdf_cond : "A==1'b1"
intrinsic_rise : 0.38;
intrinsic_fall : 0.15;
rise_resistance : 0.1443;
fall_resistance : 0.0589;
slope_rise : 0.0;
slope_fall : 0.0;
related_pin : "EN";
}
timing() {
timing_sense : negative_unate;
when : "(B & C) &!A";
sdf_cond : "B==1'b1 & C==1'b1"
intrinsic_rise : 0.38;
intrinsic_fall : 0.15;
rise_resistance : 0.1443;
fall_resistance : 0.0589;
slope_rise : 0.0;
slope_fall : 0.0;
related_pin : "EN";
}
timing() {
timing_sense : negative_unate;
when : "(!B + !C) & !A";
sdf_cond : "(B==1'b0 + C==1'b0) & (A==1'b0)"
intrinsic_rise : 0.38;
intrinsic_fall : 0.15;
rise_resistance : 0.1443;
fall_resistance : 0.0589;
slope_rise : 0.0;
slope_fall : 0.0;
related_pin : "EN";
}
}
}
}
- Eran Vodevoz
Analog Devices Herzlia, Israel
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