( ESNUG 285 Item 5 ) ----------------------------------------------- [4/3/98]
Subject: (ESNUG 282 #3 283 #9) Anyone Using Summit/Mentor's Text->Graphics?
> What I want to know is this: Is anybody out there using the Summit
> tool, or any other tool, for real text to graphics conversion. Not just
> to capture the hierarchy of the design with a bunch of block diagrams, I
> mean real text to graphics, creating bubble diagrams from state machine
> code.
>
> - Byron Reams
> NCR Columbia, South Carolina
From: Jim Avant <javant@HomeWireless.com>
John,
Concerning Byron's question, we are currently evaluating Summit's Visual
HDL and it WILL create some pretty decent-looking schematics and bubble
diagrams from Verilog code. The state diagrams usually need some slight
clean-up work (moving text that ambiguously falls on 2 arcs). I doubt
that a generated diagram from an FSM with more than, say 2 dozen states
would be very readable at first but if you're willing to spend a little
clean-up time you could probably still get some pretty useful documentation.
Of course one could argue that state machines larger than that should be
broken up anyway but that wouldn't be me doing the arguing.
This is slightly off-subject, but in the past (at another company) I've
used the VeriBest tools to generate schematics and bubble diagrams which
it converted to Verilog code for me. After a couple of years of working
with them, the tool finally created some pretty decent code. Personally,
I like having the flexibility to enter a design in multiple ways.
Visual HDL seems to do as good a job here as VeriBest. But if you ask
me if I would pay for such a tool if the money were coming out of my own
pocket (or even out of the pocket of a small start-up company) I'd have
to say thanks but no thanks. However, if I could float a license or two
between 4 or more designers (who would actually use it), then I'd buy it.
Having said that, though, even if I had Visual HDL I would still enter
simple state machines as text and just use the tool to generate the
graphics. But for chip top-level block connectivity (instantiations
only), I would enter the design in the schematic editor.
These are my own experiences and personal opinions and I know that most
designers with my level of experience would just prefer to bang it out
in vi. So we'll just have to agree to disagree, OK?
- Jim Avant
Home Wireless Networks
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From: cmv@ancor.com (Craig Verba)
John:
At Ancor Communications, all our previous ASIC designs were done using
entirely VHDL text.
Recently, we bought Summit's Visual HDL for VHDL with a Text-to-Graphics
options. I took a design from a previous ASIC, which is to be updated and
used in our next ASIC, and imported into our new Visual design structure
using Text-to-Graphics. I created a directory ( "lib" ) in my Visual
design area, copied my textual VHDL entity and architecture into
this directory, compiled the VHDL then clicked the Text-to-Graphics
(Flowchart) option. Visual then created a flow chart diagram(s) of the
process(es) in the design. Visual created actual decision boxes, action
boxes, case statement trees and properly labeled all boxes. Visual also
created the appropriate signal declaration and logical assertation
statement for any logic not covered by the flow charted processes.
When I clicked on Generate VHDL, the code Visual created from the flow
charts it created was exactly the same as my original text VHDL. Simulation
with the original test vectors also confirmed that Visual had created an
exact match to the original VHDL. Again, all I really needed to do
was "click" the proper option and Visual did all the rest.
I have talked to another engineer in out department who has successfully
created state diagrams using Text-to-Graphics. Depending on the the number
of processes or states a particular VHDL design has in it, the created
flowchart or state diagram may not be pretty to look at, but it can be
cleaned up using by using the diagram editor. I believe Summit is working
on making the Text-to-Graphic software more "artistically" inclined.
- Craig Verba
Ancor Communications
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From: Jean-Bernard Veuthey <jbernard.veuthey@eiv.ch>
Hi, John,
I used successively SDS (Mentor), VisualHDL (Summit) and now Renoir to
describe VHDL designs.
Once you understand how one SW works, it is not a problem to use the other
ones. They are quite similar to use: graphical entry of the structure,
state machines, ... Just setup carefully the strucure of your files,
directories and libraries and chose the right packages. This is the main
challenge of those SW.
Visual has the advantage to include a simulator. But I had some problems
with the SDF file (VITAL backannotation). In a fiew hours (one or two),
the students I work with, are able to implement small designs. No very
large design experience (up to 5-6k gates).
For political and financial reasons, I'm using now Renoir. The user
interface is almost the same as Visual. The Simulator is QuickHDL (or
QuickHDLlite on PC). I noticed no major problems with the last version.
The version 3.0 seems to me a Beta release. Now it works better. I
developed designs up to 10-20 kgates.
In summary, you need almost no time to learn the user interface (intuitive).
Just be carefull with the setups. The big advantage is that you don't need
to write the whole structure of your design (automatically generated), and
when you change something in the structure, it's easier to propagate the
modifications through the design (graphically).
For large designs, the main problems will come from the synthesis tools!
That's another challenge.
- Jean-Bernard Veuthey
Ecole d'Ingenieurs du Valais Sion, Switzerland
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From: verschue@eb.ele.tue.nl (Ad Verschueren)
John,
Check out our *freeware* 'Interactive Design & Simulation System' at
http://www.eb.ele.tue.nl/proj/idassfly.html :
- Interactive graphical/textual design entry
- Continuous simulation of the design *during entry*
- Fully retargettable (and synthesizable) (V)HDL generation
- Easy to learn/use (we use it in 1st trimester university courses)
- Handles complex designs like ATM switches or superscalar OOO processors
and
- It's freeware!
OK, we wrote it, so we are a bit biased - use it ourselves though (fun!)
Currently, only Compass VHDL checked to be synthesizable (but includes
generation of shell scripts for RAM/ROM macrocell generation and pad ring
creation - 'no errors, no warnings' from *our* Compass system).
Also it runs on bare bones PC only in an ancient (but extremely stable)
dialect of Smalltalk. Have fun!
- Ad C. Verschueren
Eindhoven University of Technology Eindhoven, Netherlands
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