( ESNUG 283 Item 9 ) ------------------------------------------------ [3/5/98]
Subject: (ESNUG 282 #3) Anyone Using Summit/Mentor's Text->Graphics Tools?
> ... If these examples of mixed blocks of VHDL and Verilog continue to turn
> up, don't you think designers will begin solving the problem this way?
> Or, alternatively, use a product like Renoir to convert the unfamiliar
> language IP block to graphical form and then recompile in their language
> of choice?
>
> - Wally Rhines, CEO
> Mentor Graphics
From: "Reams, Byron" <byron@xgate.columbiasc.ncr.com>
John,
I'm curious... Is anyone out there really doing that? By that I mean
are the tools mature enough that they can actually capture the design
(ie. state machines, flow charts, truth tables, etc.) correctly without
alot of hand-holding (or even with alot of hand-holding for that matter).
I know Mentor was promising that the next release of Renoir would attempt
this but the current version only builds block diagrams from the structural
elements of the code. I know that Summit claims to be able to do it.
What I want to know is this: Is anybody out there using the Summit
tool, or any other tool, for real text to graphics conversion. Not just
to capture the hierarchy of the design with a bunch of block diagrams, I
mean real text to graphics, creating bubble diagrams from state machine
code.
- Byron Reams
NCR Columbia, South Carolina
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