( ESNUG 282 Item 6 ) ------------------------------------------------ [2/26/98]
Subject: (ESNUG 278 #7 280 #4 281 #2) Synch Resets Combined W/ Random Logic
> process (clock, reset)
> begin
> If reset = '1' then
> A <= '0';
> elsif clock = '1' and clock'event then
> A <= Input1;
> B <= Input2;
> endif;
> end Process;
>
> If you elaborate the above without adding process-specific attributes
> or changing the default value, you will find design compiler DOES NOT
> NECESSARILY recognize either a synchronous or async reset. The reason
> is the code attempts to infer a synchronous reset, but the variable
> precludes it. ....
>
> - Jeff Koehler
> Cabletrons Systems Littleton, Massachusetts
From: Ed Bender <bender@atitech.ca>
Sorry to nitpick but this code looks like it is attempting to infer an
asynchronous reset, not a synchronous reset. If you want a synchronous
reset then 'reset' should NOT be in the sensitivity list:
process (clock)
begin
If reset = '1' then
A <= '0';
elsif clock = '1' and clock'event then
A <= Input1;
B <= Input2;
endif;
end Process;
Regards,
- Ed Bender
ATI Technologies Inc
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