( ESNUG 282 Item 2 ) ------------------------------------------------ [2/26/98]
Subject: (ESNUG 281 #9) Why Design_Analyzer Works Faster In The Background?
> I have run optimization of my design (written in VHDL, works fine) using
> Design Analyzer in the background. Why? Because it ties our machine
> for at least 2 days if I execute it in the foreground. DA's graphics
> aren't that involved; why does it chow so much time?
>
> - P.J. Chose
> Memorial University (Canada)
From: Ed McGettigan <ed.mcgettigan@xilinx.com>
Why are you bothering with Design Analyzer at all? Just use dc_shell
instead. I only startup DA when the boss comes around and wants to
look at a schematic for some arcane reason. :)
>When I do a report_area, I get the following messages.
>
> Information: This design contains unmapped logic. (RPT-7)
> Information: This design contains black box (unknown)
> components. (RPT-8)
>
> - P.J. Chose
> Memorial University (Canada)
This means that at least one of your modules had a problems when it was
compiling and it still has unmapped logic in it, check the log file for
errors. Another possibility is that your VHDL code contains logic that
does not exist in the target library. A D Flip/Flip with asynchronous
clear and preset for instance.
The black box warning indicates that an component that you instantiated
did not have a corresponding cell in the target library or within the
supplied VHDL code. An interface mismatch may also be a culprit here,
forgetting a port, an additional port, different bus width, etc...
To find out which entities/components are the offending ones use
check_design or link *
In addition, to speed up your compile times I would suggest that you
use a bottom-up compile approach and apply dont_touch'es as you go, unless
you want to pop for new UltraSPARC 300MHz box with 2 GIGs of RAM. :)
For a bottom-up compile you start from the lowest level module,
use "current_design [design_name]" and compile it with medium effort,
use "compile -map medium". Then instruct Synopsys not to touch it again,
use "set_dont_touch current_design", before preceeding to the next one.
This will result in much smaller memory needs and design space exploration
especially if you are using the same module multiple times. The tradeoff
is that you may lose performance or area since you aren't compiling across
module boundaries. These problem areas can be easily identified with
report_timing and fixed with incremental compiles, use
"compile -incr -map high"
- Ed McGettigan
Xilinx Inc.
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