( ESNUG 282 Item 1 ) ------------------------------------------------ [2/26/98]
Subject: (ESNUG 281 #11) Problems Cleaning Up Dangling Gates In An IP Core
> In my design, I have a bunch of gates whose outputs are not being used.
> (A purchased core that has functionality, and thus outputs, that I don't
> need is a common way that I get dangling gates.) Are there switches in
> DC to tell it only to remove extra gates & not further optimize? I tried
> "-incremental". I tried "-incremental -only_design_rule". But DC always
> insists on further "optimizing" other logic. I added
>
> "compile_no_new_cells_at_top_level = true"
>
> (for flat designs), which was successful on some modules, but
> optimized-out needed buffering on other modules. Any ideas, anyone??
>
> - Rick Weiss
> NABLE Technologies Cupertino, CA
From: Gilbert Nguyen <imgn_1@yahoo.com>
Try:
set_unconnected { your unused out_ports }
compile -only_design_rule
This should remove the unused gates at that level of hierarchy.
If it is a submodule or component underneath then:
characterize -connections your_ipcore
current_design ipcore_ref
compile -only_design_rule
To verify that the attributes are on your ports do:
get_attribute {your unused out ports } output_not_used
Regards,
- Gilbert Nguyen
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