( ESNUG 281 Item 3 ) ------------------------------------------------ [2/19/98]
Subject: (ESNUG 278 #2) Coding State Machines With Graphical Entry Tools
> I used to code in text-only VHDL and Verilog. I found using a graphical
> entry tool such as Summit's Visual or Mentor Graphics' Renoir increased
> productivity quite a bit.
>
> Visual HDL from Summit ( www.summit-design.com ) is a VHDL front-end tool
> using graphical design methods such as block diagrams, state machines,
> flow charts and truth tables to generate synthesizable HDL code that is
> optimized for specific synthesis tools (Synopsys, etc.)
>
> - Frederick K. Best
> Lockheed Martin
From: "Wayne Bell" <wbell@nortel.ca>
Hi John.
I've used Summit's tool (Visual HDL for Verilog) fairly extensively in the
last year and I have mixed feelings about the whole thing. It is *very*
easy to generate a signicant amount of 'dead' gates (conditions that cannot
be evaluated) using Visual HDL. This stems from the way state transitions
are generated into Verilog, with implicit default conditions added to the
code. These can be implied from the priority of the transactions and don't
show up on the state diagrams, but can be found on code inspections (which
I *strongly* recommend until you're very familiar with the tool!). The
superfluous code can impact Synopsys compile times, although I don't have
direct numbers for the compile time difference (the additional problem of
untested gates is a whole other issue). Having said all this, once the tool
behaviour is understood, it is extremely easy to generate complex behaviour
quickly, and more importantly, it is trival to make changes (graphical editor
and all that). I don't want to make this into a Visual HDL critique, but it
is also worth noting that I did find a few significant bugs in earlier
releases (4.1.058 to be precise) and in uprevving to 5.1, mostly in the
version control stuff, but to their credit, Summit support staff did get
things straightened out pretty quickly.
- Wayne Bell
Nortel
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