( ESNUG 281 Item 2 ) ------------------------------------------------ [2/19/98]
Subject: ( ESNUG 278 #7 280 #4) Synchronous Resets Combined W/ Random Logic
> What is the "proper" format for a clock-enabled DFF with a synchronous
> reset. The trick is to insure that the synthesizer (Synopsys) doesn't
> combine the synchronous reset with other logic that results in the
> classic "I can't get out of reset, my circuit is all Xes" problem.
>
> - Eric Ryherd
> VAutomation Inc. Nashua, NH
From: jychen@njrs.com (Joey Chen)
Hi, John,
To get around the simulator's limitation, I usually just have:
compile_preserve_sync_resets = TRUE
set in my .synopsys_dc.setup file, and DC will not synthesize combined
reset logic as long as you put the reset signal as the highest priority
condition.
- Joey Chen
NJR Corp.
---- ---- ---- ---- ---- ---- ----
From: <koehler@dechub.lkg.dec.com> (Jeff Koehler)
John,
In response to (ESNUG 278 #7), I have another related warning for designers.
As a VHDL user, I quickly recognized the situation spelled out by Sean
Atsatt (ESNUG 280 #4):
> process (clock, reset)
> begin
> If reset = '1' then
> A <= '0';
> elsif clock = '1' and clock'event then
> A <= Input1;
> B <= Input2;
> endif;
> end Process;
What I recently discovered is that you must take heed that the default
setting of the 'hdlin_ff_always_async_set_reset' variable is "TRUE"
(see the VHDL Compiler reference manual: search for that variable name).
If you elaborate the above design without adding process-specific attributes
or changing the default value, you will find that design compiler DOES NOT
NECESSARILY recognize either a synchronous or async reset. The reason for
this is the code attempts to infer a synchronous reset, but the variable
precludes it. This perpetuates the X problem since the compiler doesn't
even know you want the term to be a reset, and may feel free to rearrange
the gates for other reasons.
Rather than assume I know what a later user will set these dc variables to,
I think I will now choose to embed the process-specific attributes in my
code to ensure the intended reset is synthesized correctly. This, of
course, makes for unportable synthesis -- but gives a clear suggestion to
a later user of the code (reuse, reuse, reuse).
- Jeff Koehler
Cabletrons Systems Littleton, Massachusetts
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