( ESNUG 280 Item 4 ) ------------------------------------------------ [2/12/98]
Subject: ( ESNUG 278 #7 ) Synchronous Resets Being Combined W/ Random Logic
> What is the "proper" format for a clock-enabled DFF with a synchronous
> reset. The trick is to insure that the synthesizer (Synopsys) doesn't
> combine the synchronous reset with other logic that results in the
> classic "I can't get out of reset, my circuit is all Xes" problem.
>
> - Eric Ryherd
> VAutomation Inc. Nashua, NH
From: Sean Atsatt <sean@sierraimaging.com>
Howdy John,
There seems to be some confusion from other readers about why the "I can't
clear Xes in synchronous clear flops" problem occurs. In a simple example
that will explain how it occurs. ( I also use this as an interview question
if someone says they know all the tricks. )
1. Note that synch flops hold there state by continous feedback on each
clock of the current state in non gated clock designs.
2. A synchronous reset can be implemented by "ANDing" in an active low
reset signal right on the D input of the flop.
3. Now think of the truth table for "AND" and it is obvious that A
"and" B is equal to the not of the sum of the 3 permutions that
do not result in a 1. That is AB =3D !(!AB + A!B + !A!B). While
this contains redundant logic it is true.
4. Assume that Synopsys for other portions of the circuit has created
!AB + !A!B, and the term !A!B. When it comes time to create AB, it
finds it can do it with a "NOR" gate by "NORing" together the other two
terms it already has (assume it is driven by area and NOR is smaller
than an AND which it usually is). This creates the equation given in
step 3 above.
5. Note that for equation given in step 3 if one of the terms is an "X"
the result of AB will always be "X" even if the other term is "0".
6. Given that Synopsys creates a synchronous clear flop which uses logic
similar in nature to that above to implement the synchronous clear,
the simulator will be unable to gate the initial value of "X" to zero.
We asynchronously clear all control logic flops in our designs, in part
to avoid this problem. The increase in gate count, even across large
designs, is in the noise.
On a similar subject, given that you are not going to asynchronously clear
data path flops, the designer needs to be careful to separate them out into
different VHDL processes. I'm sure there is a Verilog equivalent, I'd just
have to go get a book out to remember the syntax. If you don't separate
them out you will instantiate unintended logic.
process (clock, reset)
begin
If reset = '1' then
A <= '0';
elsif clock = '1' and clock'event then
A <= Input1;
B <= Input2;
endif;
end Process;
In the code snippet above the B flop will have the equivalent of a sample
enable, controlled by reset which often is more logic than just reseting it.
(When reset is true B must be told to keep its old value.) You have also
placed synchronous timing requirements on your reset.
- Sean Atsatt
Sierra Imaging
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