( ESNUG 278 Item 7 ) ----------------------------------------------- [1/28/98]
From: Eric Ryherd <"vauto@tiac.net">
Subject: Avoiding Synchronous Resets Being Combined With Other Random Logic
> What is the "proper" format for a clock-enabled DFF with a synchronous
> reset. The trick is to insure that the synthesizer (Synopsys) doesn't
> combine the synchronous reset with other logic that results in the
> classic "I can't get out of reset, my circuit is all Xes" problem.
>
> - Eric Ryherd
> VAutomation Inc. Nashua, NH
From: Darrell Stewart <dstewart@nortel.ca>
Along with your synopsys sync_set_reset compiler directive, make sure that
you compile using the option: compile_preserve_sync_resets = "true"
- Darrell Stewart
Nortel
---- ---- ---- ---- ---- ---- ----
From: Bob Flatt <bobf@fishes.com>
Seems you'd have to code with clock enable dominant, and reset as a
boolean lump. To prevent that boolean lump getting merged with its fanin
(and your reset problem) you'd have to mark the D input to the reset
lump as critical or don't touch or whatever your specific synthesizer
uses to say keep a combinational net.
I'd probably use async reset, but maybe that isnt available to you.
- Bob Flatt
---- ---- ---- ---- ---- ---- ----
From: Richard Schwarz <APS@associatedpro.com>
I guess I am not quite sure what the problem is you are describing. The
code below describes a synchronous priority encoded process which should
reset if a clock comes along when a reset is set to one. This presupposes
that the reset pulse is longer than the clock period however, or that it was
generated with the clock. An asych signal shorter than the clock period
could easily be missed or ignored.
data_register:PROCESS(clk) -- Create the register
BEGIN
if (clk'event and clk='1') then
if (ce='0') then -- clock enable
q <= q;
elsif (reset='1') then -- synch reset
q <= '0';
else
if (a='1' AND b='1' AND c='1' AND q='1') then
q <= d; -- ugly logic w/ feedback
elsif (a='0' OR b='1' OR d='1' OR q='0') then
q <= c;
elsif ((a='1' AND c='1') OR (d='0' AND q='1')) then
q <= b;
else
q <= a XOR q;
end if;
end if;
end if;
END PROCESS;
What is your indication that anything is wrong? You mentioned synthesis
above and also X's, which to me means simulation. Are you having
problems simulating?
You could have also added the reset to your sensitivity list and then
done this:
if (reset'event and reset='1') then ...
This would essentially be an async reset though. Or your could use a wait
statement in combination with some combinatorial reset logic, and eliminate
the sensitivity list.
- Richard Schwarz, President
Associated Professional Systems (APS) Abingdon, Maryland
---- ---- ---- ---- ---- ---- ----
From: Eric Ryherd <"vauto@tiac.net">
Actually, the best answer is to put the sync reset first followed by the
clock enable. Synopsys recognizes the reset and most ASIC libraries have
DFFs with reset overriding the clock enable.
Turns out that Exemplar Galileo will use the clock enable of Xilinx XC4000
families with the reset as the first IF by gating RESET and clock enable
together and connecting that to the CE pin of the DFF in the FPGA.
This is exactly the result I am looking for, Synopsys is certain to produce
sync resets so we don't get stuck in Xes forever (because synopsys is
notorious for feeding Q and Q_BAR back into the "ugly" logic unless it
recognizes the sync reset attribute) and Exemplar uses the CE on FPGAs which
saves many many LUTs which are often in short supply.
Thanks to all who responded...
- Eric Ryherd
VAutomation Inc. Nashua, NH
|
|
