( ESNUG 278 Item 5 ) ----------------------------------------------- [1/28/98]
Subject: JTAG, Board Testing, And Increased Costs Of Silicon
> I just started to evaluate boundary scan (JTAG) for debug and for
> manufacturing test reasons. Quite often you can read how great it is and
> what it can do, but I am wondering if this methodology is already adopted
> by the whole industry. Here some points:
>
> 1) Has anybody an opinion on the availability and reliability of
> BSDL files?
>
> 2) Has anybody good or bad experience with "JTAG-tools" especially
> for PCB-debugging? (Do they pay back?)
>
> 3) As I started to evaluate my system to get an idea what fault
> coverage I can get on interconnection faults. I was surprised how
> low it was (20-30% -- pls note, it was not a DFT design ). Anybody
> out there who has used boundary scan for board level testing and
> could achieve significant advantages?
>
> - Joerg Grosse
> Tait Electronics Ltd., Christ Church, New Zealand
From: daveb@iinet.net.au (David R Brooks)
In my experience, availability and reliability of BSDL files is very
disappointing. A recent project included a CPLD device, which is in-system
programmed via the JTAG chain. The CPLD software requires a BSDL file for
each device in the chain, so it can bypass the other devices. Having just
one device unsupported in this way (as was the case) means the chain cannot
run. I worked around by adding a jumper to bridge out the offending device
while programming, but it shouldn't be necessary.
I agreed on the low coverage (the 20-30 % coverage you mentioned.) Many
programmable devices now come with JTAG, and a few (a very few) CPUs. Bus
drivers are available, but costly. The big sticker is memory: the market is
so competitive they won't spring for the extra silicon to implement JTAG.
The only use I have found for JTAG (and it's a very valuable one) is to
in-system program flash ROMs (and CPLDs). The ROM-programming technique
works by re-programming a FPGA to take over the system and control the ROM.
It's documented on my website <http://www.iinet.net.au/~daveb>. Follow
the "Free Stuff" pointer.
- Dave Brooks
iiNet Technologies
---- ---- ---- ---- ---- ---- ----
From: Todd <tdh@io.com>
FWIW, in one of last year's issues of Electronic Engineering Times, there
was an article on how pitiful JTAG implementations are across the industry.
It was written either by, or sourced from someone at HP.
Wow... EE Times has a nice web site. I was able to find the article
fairly easily:
Title: IC makers blasted for failure to back boundary scan
Author: Stan Runyon
Date: December 01, 1997, Issue: 983
Search their archives here to get the complete article text:
http://techweb.cmp.com/eet/news/search/print.html
- Todd
io
---- ---- ---- ---- ---- ---- ----
From: "Ross Swanson" <swan000@erols.com>
It depends on the system that JTAG is in, the military has produced some
system's where all the ASIC's use JTAG and so board level inner-connect
testing is a snap. However JTAG isn't going to pay for itself if the system
around the chip doesn't support this methodology. I believe some large
chip's are setup to use the JTAG port as a debugging tool for S/W, providing
single step, readback and download.
- Ross Swanson
---- ---- ---- ---- ---- ---- ----
From: "Alvin E. Toda" <aet@lava.net>
Joerg Grosse wrote:
> 3) As I started to evaluate my system to get an idea what fault coverage I
> can get on interconnection faults I was surprised how low it was (20-30%
> -- pls note, it was not a DFT design ).
This is not surprising if as you say it is "not a DFT design". Question
on your analysis, though. As you able to model all components on the
board which have NO boundary scan? If not, then a great number of the
inconnections on the board would be untestable nets. I believe a number
of software programs report the fault coverage on the number of nets
that are TESTABLE.
I believe you need to bring the state on untestable nets -- such as outputs
of non-modeled components -- to KNOWN states by exercising the board. If
all untestable nets can be brought to know states such as through a bed of
nails technique if not through exercise of the circuit, then I'm sure that
the fault coverage of the testable nets by the scan logic would be MUCH
greater.
Generally, fault coverage fails on components such as unscanned flip flops
and asynchronous sequential logic. Even here, it would seem that if you
were by some means to define these outputs than the coverage would be higher.
It seems a lot of a test engineer's time is spent in getting a stimulus to
a certain node. With partial scan, there is still this necessity. I don't
think you can develop a scantest ONLY using the scan logic if you insist
("no DFT") on using partial scan.
- Alvin E. Toda
2-Sigma Pearl City, Hawaii, USA
---- ---- ---- ---- ---- ---- ----
From: "Gerhart Hlawatsch" <ghl@uni-muenster.de>
The boundary scan story is still not settled in industry. Initially
intended to be implemented in complex circuits for manufacturing tests and
enhanced subsequently to allow PCB fault detection several drawbacks arose.
The intest (internal function test) needs a large test vector file for
the mega-gate chips and take too long for an economic production. Instead,
special test functions like a signature verification are preferred.
The extest (external signal path test) is a beautiful feature to detect
PCB faults (open circuits or shorts). Up to date, however I do not know
of any chip manufacturers which have I/O-pads with boundary scan function
integrated in the pad logic. Therefore you have to increase the core of
the chip which can - with core limited designs - lead to a larger silicon
area and thus to higher cost.
A few years ago the FPGA and CPLD inustry detected the JTAG boundary scan
interface for in-system programming of the eeprom switch matrix of the
device. Surely a good draw. Texas Instruments has bus drivers and other MSI
chips with JTAG. Using these raises the total system cost by 10 or 20 %.
A detailed description of JTAG boundary scan applications will be found
in http://www.goepel.com/
Have fun!
- Gerhart Hlawatsch
Westfaelische Wilhelms-Universitaet Muenster, Germany
---- ---- ---- ---- ---- ---- ----
From: Frank Bouwman <Frank.Bouwman@sv.sc.philips.com>
Gerhart Hlawatsch wrote:
> The extest (external signal path test) is a beautiful feature to detect
> PCB faults (open circuits or shorts). Up to date, however I do not know
> of any chip manufacturers which have I/O-pads with boundary scan
> function integrated in the pad logic. Therefore you have to increase the
> core of the chip which can - with core limited designs - lead to a larger
> silicon area and thus to higher cost.
I always hear the phrase: larger silicon THUS higher cost.
I hear it for full scan, boundary scan, ...
Extra silicon may be a cost for producing it, but it is going to pay back
BIG if you run into problems with a new design and need for example debug
or fault localization capabilities. Do you know what it costs to delay
market introductions ?
- Frank Bouwman
Philips Semiconductors
|
|
