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Subject:  Facing Problems With The Xilinx-Synopsys Interface (XSI)

> I'm having some problems with the XSI (Xilinx Synopsys Interface). I
> have the Synopsys and XSI installed on a Sun Workstation but the XACT6 /
> Foundation Series is installed on a PC. As I don't have the license to
> use VHDL from Xilinx, I'm using the Synopsys tools to implement the
> "modules" of my design. The documentation describes the whole process of
> implementing designs in Synopsys and how to export the XNF file
> generated (using syn2xnf, etc...) to the Xilinx tools, so that one can
> place and route the design. But it assumes that the design is a
> top-level one, that is, it contains PADS and the signals are connected
> in some way to the external pins. In my case, I want to generate blocks
> (known as "macros") and place them in my schematic (Foundation Series)
> so that I can make the interconnections mannualy.
> I can successfully import the xnf generated by Synopsys and translated
> by the SYN2XNF from XSI into the schematic, but when I try to Place and
> Route something goes wrong and I receive dozens of warnings and PPR
> errors.  Please, if someone can help me, do it !
>
>   - Rodrigo Cesar de Moraes Tavares
>     Universidade Federal de Minas Gerais, Brasil


From: Terry Graessle <graessle@vlsiDOTgsfc.nasa.gov>

Use the -sub command line option with syn2xnf:

  syn2xnf -sub xxxx.sxnf

This tells syn2xnf that the design is a subcircuit & not at the top level.

  - Terry L. Graessle         
    Lockheed Martin - Space Mission Systems

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From: Brian Philofsky <brianp@xilinx.com>

Rodrigo,

    Take a look at http://www.xilinx.com/techdocs/2450.htm  This tells you
how to import a Synopsys design into Viewlogic but Foundation should be
similar.  Things to note, change part 1 about the part changing the bus
naming style to:

    bus_naming_style = "%s<%d>"
    bus_dimension_separator_style = "><"
    bus_inference_style = "%s<%d>"

I belive Foundations uses angle brackets (<>) as bus separtors.

Also, the creation of the symbol would be slightly different but I do not
have the details on this.  Do not beleieve it would be too hard to figure
out though.

I am guessing that the problem you were having before is maybe you did not
specify the -s switch when you ran syn2xnf specifying this is a
sub-module.  Without the switch, SYN2XNF will place EXT records in the XFF
file and possibly cause the problems you were seeing.

  - Brian Philofsky
    Xilinx

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From: Bill Lenihan <lenihan3we@earthlink.net>

I've done this with Synopsys FPGA Compiler & Mentor tools, all on a
workstation.  If you use different schematic & simulation tools some details
will likely differ, but the principle may remain the same.

 1) Synthesize your HDL module(s) in Synopsys, and save as <design>.sxnf
    files in "xnf" format. If the top level schematic has timespecs, make
    sure you "remove_constraint -all" in synopsys, otherwise the timing goals
    you set in Synopsys will get passed into the sxnf file and may conflict
    with the timespecs you set in your (higher level in the heirarchy)
    schematic.

 2) Run the syn2xnf conversion utility (use -help to see all the switches
    you must set) to produce the <design>.xnf and <design>.xff files.  Copy
    the <design>.xff to <design>.xnf in the directory that has the main
    (schematic) design.  Make sure you have a symbol created for the
    HDL-based components (no underlying schematic will exist, yet, for these
    symbols).  Aside from the usual attributes on these symbols, they should
    also have "FILE = <design>.xnf" attributes, too.  This associates the
    synthesis-generated .xnf file with the symbol and keeps men2xnf from
    trying to generate an xnf netlist from a schematic that doesn't exist.

 3) From here, the xmake design flow continues as before.  The Mentor-Xilinx
    design flow does generate a schematic for the synthesis-based components,
    but this is just to keep the simulator happy and this schematic is quite
    un-readable.

I have complained about this before to Synopsys & Xilinx.  Namely, that most
HDL tutorials show the flow for complete-HDL designs, yet HDL newbies start
off doing a little bit of HDL in an otherwise schematic design, and
tutorials should be written with this in mind.  A Synopsys FAE wrote to
agree with me and take it to the powers that be at Synopsys.  My response
from Xilinx was, of course, silence.

  - William Lenihan
    Hughes