( ESNUG 275 Item 9 ) --------------------------------------------- [12/17/97]
From: rmehler@netcom.com (Ron Mehler)
Subject: Ron Mehler's Quickie Hierarchical "Characterize" Tutorial
John,
I don't suppose I've discovered anything that isn't already well known, but
for what it's worth, here's my "characterize" tutorial I used successfully
at Alcatel. The methodology:
1: compile designs up the tree
2: characterize down
3: compile from the top for design rule changes only
A
________|________
| B | C
------ --------
| | | |
D E F G
For example, a design consisting of the above tree would have the script:
compile D
compile E
compile F
compile G
compile B
compile C
compile A
characterize{B C}
current_design = B
characterize {D E}
current_design = C
characterize {F G}
current_design = A
compile -only_design_rule
This methodology does not produce the desired results. Design constraints
applied at the top level were not applied to lower levels, resulting in
unacceptable fanout and other design rule violations.
It was decided to implement the approach illustrated by Glenn Dukes in
"Synopsys dc_shell Scripts for Synthesis Application Note" of February 1993.
Scripts were written to perform the following operations automatically on
any design hierarchy:
current_design = A
characterize B
write_script B.wscr
characterize C
write_script C.wscr
current_design = B
characterize D
etc. through the entire hierarchy... then compile from the bottom up:
current_design = G
include G.wscr
compile -only_design_rule
. . .
current_design = B
include B.wscr
compile -only_design_rule
current_design = A
compile -only_design_rule
This appears to produce the desired results, after patching them up to work
around Synopsys bugs.
David Moreland (David.Moreland@Eng.Sun.COM) also has noted that timing
constraints are not always pushed down when blocks are characterized. He
has proposed the following script to ensure that all submodules get
default constraints:
find(design,"*")
des_list = dc_shell_status
foreach (DES, des_list) {
current_design = DES
filter all_inputs() "@max_transition==0"
if (dc_shell_status != "") {
set_max_transition 3.0 dc_shell_status
}
}
Another problem we have noted here is Synopsys putting in delay lines on
flip-flop feedback lines when using clock uncertainty. To get around this
problem, an engineer here proposed adding the following script:
foreach(dummy, all_registers()) {
set_false_path -hold -from dummy -to dummy
}
and then compiling incrementally.
This appears to produce the desired results on small files, but causes
large ones to spin, more or less, forever. For now, we have decided that
we can live with those extraneous delay lines.
I invite more discussion about hierarchical synthesis on ESNUG.
- Ron Mehler
Consultant
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