( ESNUG 275 Item 8 ) --------------------------------------------- [12/17/97]
Subject: ( ESNUG 274 #3 ) Synopsys Products & Their Revision Schedules
> Now they are making a _BIG_ deal out of the new "PrimeTime" product.
> They admit that the timing analyzer in Design Compiler just isn't good
> enough for 0.25 micron and beyond. So they are working to fix it, right?
> WRONG, silicon breath, they are providing a _NEW_ tool for new licensing
> fees and leaving the old timing analyzer in DC.
>
> - [ You've Hit My _HOT_ Button ]
From: catapano@anasazi.sps.mot.com (Patrick Catapano)
John,
Nice HOT button letter from "[ You've Hit My _HOT_ Button ]".
oe's media
insuring that the features we currently use are up to date and that
"evolutionary" improvements (improved static timing is a good example) are
part of that money. Revolutionary features (placed-based synthesis for
example) can, and should, be price-listed.
What I'd like to see is the notion of Infra-structure in the EDA industry.
Infra-structure is NOT a line-item... no matter how a salesperson envisions
it! They have a new database for speedup and data management and <put
feature here>? Fine. It won't, and shouldn't be, in the pricelist.
Now the hard part! Convincing the EDA company that static timing in a
synthesis tool is infra-structure, as is autoplacement in a P&R tool.
I think we can convince them, btw. We were successful in removing
performance-based pricing. Remember the days when licenses for faster boxes
cost more? Turns out we COULD'VE done more chips, but, we always did ALL
the chips.
- Patrick Catapano
Motorola
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From: [ Anon E. Mouse ]
John, pls call me Anon E. Mouse.
Re Comments from "You've Hit My _HOT_ Button", I feel much the same when I
read the recent press releases and brochures for Module Compiler. The
Synopsys brochures & sales pitches have always given the impression that
Design Compiler / FPGA Compiler / Behavioral Compiler are capable of (and
responsible for) synthesizing datapath logic as well as random/control logic.
So I expect improvements in synthesis of any type of logic to be ADDED to
DC/FC/BC. If it is an evolutionary improvement, then add a small price
increase to DC/FC/BC. If it is a revolutionary improvement, then add a
substantial price increase to DC/FC/BC.
I suspect that the problem is that Synopsys is afraid that a revolutionary
feature won't look so revolutionary if it is tagged onto the same old
DC/FC/BC, so they may feel the need to emphasize its' worth by marketing it
as a new tool. The problem is that this demonstrates a lack of respect for
their customer's other main cost driver: learning new tools and languages.
- [ Anon E. Mouse ]
> In 1996 we received 4 software releases. In 1997 there are going to be
> only 2 software releases: 1997.01 and 1997.08. Are we paying 1/2 the
> maintenance? No, we are just getting 1/2 of the updates. Then again,
> maybe this isn't all bad. They'll have time to test the software instead
> of having the users do it.
>
> - [ You've Hit My _HOT_ Button ]
From: landmh@taec.com (Howard Landman)
John,
I'd guess I'm a couple of revs behind. I must be cutting edge. :-)
But seriously, it takes time to catch the whole methodology up. Our library
guys in Japan should probably be using Unigen ("4.0") library format, but
they're not, because they need to rewrite all their library generation
scripts. You *can't* jump blindly on the latest rev of everything,
*especially* if you have to pay for it. HAL got burned by moving onto the
latest Mentor software too quickly -- a lot of it just flat didn't work
yet -- and they shelled out "mondo dollars" for it, too. You think Mentor
is going to give them their money back just because the software is broken?
And what little time I do have for learning new Synopsys features has
to be spent on the most important problems. For me, that means evaluating
PrimeTime and ECO Compiler.
I have no time for a new rev every 3 months.
- Howard Landman
Toshiba
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