( ESNUG 274 Item 2 ) --------------------------------------------- [12/10/97]
Subject: ( ESNUG 272 #9 273 #3 ) Floating DW Inputs, & Module Compiler
> I am using Design Compiler for my synthesis in VHDL. I have a matrix
> multiplication in my design. It is a 3 by 3 matrix. My coefficients as
> well as the inputs are signed. For one sum of partial products I use:
>
> a <= signed(c1) * signed(in1) +
> signed(c2) * signed(in2) +
> signed(c3) * signed(in3);
>
> Q1) DC does not recognize "signed" and thus when it uses designware for
> the mutlipliers, it does'nt connect the "TC" (two's complement) to high
> -- it just lets it float. (Floating inputs??!!!) The way I got around
> it is to instantiate the DW02_mult and "force" the TC bit high. Is
> there any other, more automatic way to solve this problem beyond hand
> instantiating & baby-sitting DW parts?
>
> Q2) When I use the above equation, I break it into partial products, i.e.
>
From: "Peter A. Ruetz" <PeterRuetz@california.com>
John,
This does not answer the question directly, but have you tried using Module
Compiler? It excels at arithmetic computations like FIR filters and matrix
multipliers and handles signed/unsigned data correctly and easily.
Something like the inner product above is coded as:
wire signed [ ] in1,in2,in3;
...
A=c1*in1+c2*in2+c3*in3;
MC does not use DesignWare, and hence there should be no trouble with TC
control signals. It builds the multipliers optimized for the types of
inputs provided (any combination of signed and unsigned) rather than trying
to optimize a programmable multiplier with a TC input. Hence, when you
change the formats in the wire declaration, the multipliers change
automatically.
I have used MC quite a bit and have had success with circuits like this.
Note: you can't enter VHDL, though, it has it's own language. Although it
is a "non-standard" language, you can quite efficiently describe most
datapath type problems (like the one above).
Just an idea,
- Peter Ruetz
Ammonite Design Systems
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