( ESNUG 273 Item 8 ) --------------------------------------------- [12/5/97]
Subject: ( ESNUG 271 #6 ) Infinite Loops During Designware Mapping !!
> We ran into infinite loops during Designware mapping for some of the
> designware component (DW01_incdec, DW01_GP_SUM) of 97.01 and 97.08.
>
> Our current workaround is dont_use them from Designware library, and I am
> waiting for more information from Synopsys. However, I want to know if
> any designers have seen the same problem or any other workaround.
>
> set_dont_use (standard.sldb/DW01_incdec)
> set_dont_use (standard.sldb/DW01_GP_SUM)
From: "Yuan (Steve) Hwang" <hwang@eng.adaptec.com>
John, here's a follow-up to this DW infinite loop problem.
The infinite loop is caused by some area optimization that Design Compiler
does by default. This problem has been fixed for the next release of DC
(1998.02). In the meantime, there are two workarounds:
1. Don't set_wire_load for the top level
2. Don't use the 'rpl' implementation of the DW01_incdec.
set_dont_use dw01.sldb/DW_incdec/rpl
set_dont_use standard.sldb/DW01_incdec/rpl
(There is nothing wrong with this implementation. It is just that
the area optimization algorithm is more sensitive to the structure
of this implementation.)
Regards,
- Yuan (Steve) Hwang
Adaptec
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