( ESNUG 273 Item 1 ) --------------------------------------------- [12/5/97]
From: jcooley@world.std.com ( John Cooley )
Subject: WARNING Design Compiler 97.08 Is Creating BROKEN Logic !
I just recieved a warning from my contacts within Synopsys that Design
Compiler 97.08 is creating functionally incorrect logic. (Apparently this
bug was a side-effect of Synopsys trying to speed up elaboration times
within HDL Compiler.) Currently, there are two workarounds to this bug:
1) Analyze/elaborate (or read) the design using DC 97.01. Write out the
*unmapped* .db file. Then compile the db file using DC 97.08.
2) Or, when using DC 97.08 release, set the following undocumented
variable at the dc_shell prompt *prior* to reading in the HDL source.
hdlin_turbo_sequential = false
The Synopsys people also told me that they'll be shipping a patched version
of DC 97.08 to all synthesis customers by the 3rd week of December.
- John Cooley
the ESNUG guy
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