( ESNUG 271 Item 8 ) -------------------------------------------- [11/14/97]
Subject: ( ESNUG 269 #9 ) Seeking Tips & Tricks W/ Asynchronous Synthesis
> I am trying to learn and put into "real" practice synthesizing some
> asynchronous logic using Synopsys. Do you mind giving me tips on the
> general guidelines for such designs, how to avoid any possible pitfalls,
> and any sample scripts?
>
> - Mehrdad Toofan
> SMOS
From: pbe@cs.man.ac.uk (Phil Endecott)
Dear John,
I was quite suprised to see this message on ESNUG since Synopsys is
inherently very much a synchronous tool. I'll be interested to see if
there is much followup from other readers.
The group that I work as a member of here at the University of
Manchester, England has developed quite substantial expertise in
asynchronous design. We have implemented two asynchronous versions of
the ARM microprocessor and are now working on a third; these chips
have advantages or potential advantages over their synchronous
counterparts in the areas of power consumption, electromagnetic
compatibility and possibly performance. Our current design is a
collaborative project with a German telecomms company and will end up
in some of their products.
The fact the our synchronous competitors have tools like Synopsys to
help them puts us at a disadvantage - most of our work to date has
been old fashioned manual design. Realising the problem we have put a
fair bit of effort into tools, and my work over the last couple of
years has been developing a behavioural modelling language. At
Manchester we haven't done much work on synthesis (apart from a couple
of postgraduate student projects). Others have put effort in this
direction though. Philips have an excellent system called Tangram
which has produced some really incredible results - in one case they
improved the power efficiency of an error detector/corrector chip by
two orders of magnitude over the synchronous version. Tangram's main
problem is that it is proprietry, so if you are a potential competitor
you can't have it. Another tool that also has great promise is an STG
synthesis tool called Petrify from the University of Newcastle and
others. This takes a hybrid STG/Petri Net description of a circuit
and generates a speed-independent circuit from them. This approach
works really well for smallish subcircuits (<10 gates say); for bigger
things you need to do some decomposition by hand beforehand. The
input notation also takes a bit of getting used to.
I would be very interested to hear what sort of circuits designers are
looking at. I think I have been exposed to most of the asynchronous
synthesis tools around, and I would be keen to help point them in the
right direction. You might also like to have a look at our web page:
http://www.cs.man.ac.uk/amulet
Somewhere in there you can find a list of asynchronous tools, a searchable
bibliography, links to other groups doing async. work, etc. etc.
- Phil Endecott
University of Manchester, England
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