( ESNUG 271 Item 6 ) -------------------------------------------- [11/14/97]

From: "Yuan (Steve) Hwang" <hwang@eng.adaptec.com>
Subject: Watch Out For Infinite Loops During Designware Mapping !!

John,

We ran into infinite loops during Designware mapping for some of the
designware component (DW01_incdec,  DW01_GP_SUM) of 97.01 and 97.08.

Our current workaround is dont_use them from Designware library, and I am
waiting for more information from Synopsys.  However, I want to know if
any designers have seen the same problem or any other workaround.

          set_dont_use (standard.sldb/DW01_incdec)
          set_dont_use (standard.sldb/DW01_GP_SUM)

Regards,

  - Yuan (Steve) Hwang
    Adaptec



 Sign up for the DeepChip newsletter.
Email
 Read what EDA tool users really think.


Feedback About Wiretaps ESNUGs SIGN UP! Downloads Trip Reports Advertise

"Relax. This is a discussion. Anything said here is just one engineer's opinion. Email in your dissenting letter and it'll be published, too."
This Web Site Is Modified Every 2-3 Days
Copyright 1991-2024 John Cooley.  All Rights Reserved.
| Contact John Cooley | Webmaster | Legal | Feedback Form |

   !!!     "It's not a BUG,
  /o o\  /  it's a FEATURE!"
 (  >  )
  \ - / 
  _] [_     (jcooley 1991)