( ESNUG 270 Item 8 ) -------------------------------------------- [10/31/97]
From: Anindya Saha <asaha@tif.ti.com>
Subject: A Tip When Inferring Negative Edge Triggered Flip-flops
Hi John,
If you are using some negative edge triggered flip-flop constructs in your
VHDL design of the type:
if ( clk'event and clk='0') ...
or for the Verilog users, of the type
always @( negedge clk) ...
I've found that Design Compiler sometimes creates a *rising* edge triggered
flip-flop with an inverter at the clock input instead of grabbing a negative
edge flip-flop!
My tip is that if you want to make sure you get a true negative edged flip-
flop, before compiling in DC, make sure to place a set_dont_touch attribute
on clk.
- Anindya Saha
Texas Instruments
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