( ESNUG 270 Item 4 ) -------------------------------------------- [10/31/97]
Subject: ( ESNUG 269 # 6 ) DC 97.01 & 97.08 Inconsistant W/ Bussed VHDL Ports
> When I first installed 1997.08, I did experience an inconsistency (which
> I reported to Synopsys) in versus 1997.01 with respect to how the VHDL
> writer handles bussed ports (w/ certain combinations of switch settings).
>
> When I read into 1997.08 a source VHDL file containing a vector port in
> which the LSB was non-zero, and then wrote out the same design as VHDL
> output file, it changed the range of the vector of the LSB to zero!
From: bautista@cma.ulpgc.es (Tomas Bautista)
Hi, John,
In using the Synopsys design_analyzer, I've found this bit blasting to only
be a VHDL-related problem. In my designs, every port I have inside the
design is written out all right when saving the design in a DB file or in a
Verilog one. But when saving it in a VHDL one, it splits the whole bus port
into a set of 1-bit ports. For instance, a(31:0) is translated into
a_31_port, a_30_port, and so on.
- Tomas Bautista
University of Las Palmas de G.C.
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